|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
|
#include "DQM/SiStripCommissioningClients/interface/FedCablingHistograms.h"
#include "CondFormats/SiStripObjects/interface/FedCablingAnalysis.h"
#include "DQM/SiStripCommissioningAnalysis/interface/FedCablingAlgorithm.h"
#include "DQM/SiStripCommissioningSummary/interface/SummaryGenerator.h"
#include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
#include "DataFormats/SiStripCommon/interface/SiStripEnumsAndStrings.h"
#include "DQM/SiStripCommon/interface/ExtractTObject.h"
#include "FWCore/MessageLogger/interface/MessageLogger.h"
#include <iostream>
#include <sstream>
#include <iomanip>
#include "TProfile.h"
using namespace std;
using namespace sistrip;
// -----------------------------------------------------------------------------
/** */
FedCablingHistograms::FedCablingHistograms(const edm::ParameterSet& pset, DQMStore* bei)
: CommissioningHistograms(pset.getParameter<edm::ParameterSet>("FedCablingParameters"), bei, sistrip::FED_CABLING),
factory_(new Factory) {
LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
<< " Constructing object...";
}
// -----------------------------------------------------------------------------
/** */
FedCablingHistograms::~FedCablingHistograms() {
LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
<< " Destructing object...";
}
// -----------------------------------------------------------------------------
/** */
void FedCablingHistograms::histoAnalysis(bool debug) {
LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]";
uint16_t valid = 0;
HistosMap::const_iterator iter;
Analyses::iterator ianal;
// Clear map holding analysis objects
for (ianal = data_.begin(); ianal != data_.end(); ianal++) {
if (ianal->second) {
delete ianal->second;
}
}
data_.clear();
// Iterate through map containing histograms
for (iter = histos().begin(); iter != histos().end(); iter++) {
// Check vector of histos is not empty
if (iter->second.empty()) {
edm::LogWarning(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
<< " Zero histograms found!";
continue;
}
// Retrieve pointers to histos
std::vector<TH1*> profs;
Histos::const_iterator ihis = iter->second.begin();
for (; ihis != iter->second.end(); ihis++) {
TProfile* prof = ExtractTObject<TProfile>().extract((*ihis)->me_);
if (prof) {
profs.push_back(prof);
}
}
// Perform histo analysis
FedCablingAnalysis* anal = new FedCablingAnalysis(iter->first);
FedCablingAlgorithm algo(this->pset(), anal);
algo.analysis(profs);
data_[iter->first] = anal;
if (anal->isValid()) {
valid++;
}
}
if (!histos().empty()) {
edm::LogVerbatim(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
<< " Analyzed histograms for " << histos().size() << " FED channels, of which "
<< valid << " (" << 100 * valid / histos().size() << "%) are valid.";
} else {
edm::LogWarning(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
<< " No histograms to analyze!";
}
}
// -----------------------------------------------------------------------------
/** */
void FedCablingHistograms::printAnalyses() {
Analyses::iterator ianal = data_.begin();
Analyses::iterator janal = data_.end();
for (; ianal != janal; ++ianal) {
if (ianal->second) {
std::stringstream ss;
ianal->second->print(ss);
if (ianal->second->isValid()) {
LogTrace(mlDqmClient_) << ss.str();
} else {
edm::LogWarning(mlDqmClient_) << ss.str();
}
}
}
}
// -----------------------------------------------------------------------------
/** */
void FedCablingHistograms::createSummaryHisto(const sistrip::Monitorable& histo,
const sistrip::Presentation& type,
const std::string& dir,
const sistrip::Granularity& gran) {
LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]";
// Check view
sistrip::View view = SiStripEnumsAndStrings::view(dir);
if (view == sistrip::UNKNOWN_VIEW) {
return;
}
// Analyze histograms if not done already
if (data_.empty()) {
histoAnalysis(false);
}
// Extract data to be histogrammed
uint32_t xbins = factory_->init(histo, type, view, dir, gran, data_);
// Create summary histogram (if it doesn't already exist)
TH1* summary = histogram(histo, type, view, dir, xbins);
// Fill histogram with data
factory_->fill(*summary);
}
|