|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
#include "DQM/SiStripCommissioningSummary/interface/FedCablingSummaryFactory.h"
#include "DQM/SiStripCommissioningSummary/interface/SummaryGenerator.h"
#include "DataFormats/SiStripCommon/interface/SiStripEnumsAndStrings.h"
#include "FWCore/MessageLogger/interface/MessageLogger.h"
#include <iostream>
#include <sstream>
using namespace sistrip;
// -----------------------------------------------------------------------------
//
uint32_t SummaryPlotFactory<FedCablingAnalysis*>::init(const sistrip::Monitorable& mon,
const sistrip::Presentation& pres,
const sistrip::View& view,
const std::string& level,
const sistrip::Granularity& gran,
const std::map<uint32_t, FedCablingAnalysis*>& data) {
// Some initialisation
SummaryPlotFactoryBase::init(mon, pres, view, level, gran);
// Check if generator class exists
if (!SummaryPlotFactoryBase::generator_) {
return 0;
}
// Extract monitorable
std::map<uint32_t, FedCablingAnalysis*>::const_iterator iter = data.begin();
for (; iter != data.end(); iter++) {
float value = static_cast<float>(sistrip::invalid_);
if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_ID) {
value = iter->second->fedId();
} else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_CH) {
value = iter->second->fedCh();
} else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_ADC_LEVEL) {
value = iter->second->adcLevel();
} else {
edm::LogWarning(mlSummaryPlots_) << "[SummaryPlotFactory::" << __func__ << "]"
<< " Unexpected monitorable: "
<< SiStripEnumsAndStrings::monitorable(SummaryPlotFactoryBase::mon_);
continue;
}
SummaryPlotFactoryBase::generator_->fillMap(
SummaryPlotFactoryBase::level_, SummaryPlotFactoryBase::gran_, iter->first, value);
}
return SummaryPlotFactoryBase::generator_->nBins();
}
//------------------------------------------------------------------------------
//
void SummaryPlotFactory<FedCablingAnalysis*>::fill(TH1& summary_histo) {
// Histogram filling and formating
SummaryPlotFactoryBase::fill(summary_histo);
if (!SummaryPlotFactoryBase::generator_) {
return;
}
// Histogram formatting
if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_ID) {
SummaryPlotFactoryBase::generator_->axisLabel("FED id");
} else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_CH) {
SummaryPlotFactoryBase::generator_->axisLabel("FED channel");
} else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_ADC_LEVEL) {
SummaryPlotFactoryBase::generator_->axisLabel("Signal level [ADC]");
} else {
edm::LogWarning(mlSummaryPlots_) << "[SummaryPlotFactory::" << __func__ << "]"
<< " Unexpected SummaryHisto value:"
<< SiStripEnumsAndStrings::monitorable(SummaryPlotFactoryBase::mon_);
}
}
|