Back to home page

Project CMSSW displayed by LXR

 
 

    


File indexing completed on 2021-02-14 12:47:31

0001 
0002 #include "CalibFormats/SiStripObjects/interface/SiStripFecCabling.h"
0003 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
0004 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0005 #include "FWCore/Utilities/interface/typelookup.h"
0006 #include <iomanip>
0007 #include <iostream>
0008 
0009 using namespace sistrip;
0010 
0011 // -----------------------------------------------------------------------------
0012 //
0013 SiStripFecCabling::SiStripFecCabling(const SiStripFedCabling &fed_cabling) : crates_() {
0014   LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
0015                        << " Constructing object...";
0016   crates_.reserve(4);
0017   buildFecCabling(fed_cabling);
0018 }
0019 
0020 // -----------------------------------------------------------------------------
0021 //
0022 void SiStripFecCabling::buildFecCabling(const SiStripFedCabling &fed_cabling) {
0023   LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
0024                        << " Building FEC cabling...";
0025 
0026   // Retrieve and iterate through FED ids
0027   auto feds = fed_cabling.fedIds();
0028   for (auto ifed = feds.begin(); ifed != feds.end(); ifed++) {
0029     // Retrieve and iterate through FED channel connections
0030     auto conns = fed_cabling.fedConnections(*ifed);
0031     for (auto iconn = conns.begin(); iconn != conns.end(); iconn++) {
0032       // Check that FED id is not invalid and add devices
0033       if (iconn->fedId() != sistrip::invalid_) {
0034         addDevices(*iconn);
0035       }
0036     }
0037   }
0038 
0039   // Consistency checks
0040   for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
0041        ++icrate) {
0042     for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
0043       for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
0044            ++iring) {
0045         for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
0046              ++iccu) {
0047           for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
0048                ++imod) {
0049             //@@ need consistency checks here!
0050           }
0051         }
0052       }
0053     }
0054   }
0055   LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
0056                        << " Finished building FEC cabling";
0057 }
0058 
0059 // -----------------------------------------------------------------------------
0060 //
0061 void SiStripFecCabling::addDevices(const FedChannelConnection &conn) {
0062   auto icrate = crates_.begin();
0063   while (icrate != crates_.end() && (*icrate).fecCrate() != conn.fecCrate()) {
0064     icrate++;
0065   }
0066   if (icrate == crates_.end()) {
0067     crates_.push_back(SiStripFecCrate(conn));
0068   } else {
0069     icrate->addDevices(conn);
0070   }
0071 }
0072 
0073 // -----------------------------------------------------------------------------
0074 //
0075 void SiStripFecCabling::connections(std::vector<FedChannelConnection> &conns) const {
0076   LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
0077                        << " Building vector of FedChannelConnection objects...";
0078   conns.clear();
0079   for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
0080        ++icrate) {
0081     for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
0082       for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
0083            ++iring) {
0084         for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
0085              ++iccu) {
0086           for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
0087                ++imod) {
0088             for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
0089               conns.push_back(FedChannelConnection(icrate->fecCrate(),
0090                                                    ifec->fecSlot(),
0091                                                    iring->fecRing(),
0092                                                    iccu->ccuAddr(),
0093                                                    imod->ccuChan(),
0094                                                    imod->activeApvPair(imod->lldChannel(ipair)).first,
0095                                                    imod->activeApvPair(imod->lldChannel(ipair)).second,
0096                                                    imod->dcuId(),
0097                                                    imod->detId(),
0098                                                    imod->nApvPairs(),
0099                                                    imod->fedCh(ipair).fedId_,
0100                                                    imod->fedCh(ipair).fedCh_,
0101                                                    imod->length(),
0102                                                    imod->dcu(),
0103                                                    imod->pll(),
0104                                                    imod->mux(),
0105                                                    imod->lld()));
0106               uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
0107               uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
0108               conns.back().fedCrate(fed_crate);
0109               conns.back().fedSlot(fed_slot);
0110             }
0111           }
0112         }
0113       }
0114     }
0115   }
0116 }
0117 
0118 // -----------------------------------------------------------------------------
0119 //
0120 namespace {
0121   // Using a template allows the const and non-const version to share the same
0122   // code
0123   template <typename T>
0124   auto moduleFrom(T &crates, const FedChannelConnection &conn)
0125       -> decltype(&(crates[0].fecs()[0].rings()[0].ccus()[0].modules()[0])) {
0126     std::stringstream ss;
0127     auto icrate = crates.begin();
0128     while (icrate != crates.end() && icrate->fecCrate() != conn.fecCrate()) {
0129       icrate++;
0130     }
0131     if (icrate != crates.end()) {
0132       auto ifec = icrate->fecs().begin();
0133       while (ifec != icrate->fecs().end() && ifec->fecSlot() != conn.fecSlot()) {
0134         ifec++;
0135       }
0136       if (ifec != icrate->fecs().end()) {
0137         auto iring = ifec->rings().begin();
0138         while (iring != ifec->rings().end() && iring->fecRing() != conn.fecRing()) {
0139           iring++;
0140         }
0141         if (iring != ifec->rings().end()) {
0142           auto iccu = iring->ccus().begin();
0143           while (iccu != iring->ccus().end() && iccu->ccuAddr() != conn.ccuAddr()) {
0144             iccu++;
0145           }
0146           if (iccu != iring->ccus().end()) {
0147             auto imod = iccu->modules().begin();
0148             while (imod != iccu->modules().end() && imod->ccuChan() != conn.ccuChan()) {
0149               imod++;
0150             }
0151             if (imod != iccu->modules().end()) {
0152               return &(*imod);
0153             } else {
0154               ss << "[SiStripFecCabling::" << __func__ << "]"
0155                  << " CCU channel " << conn.ccuChan() << " not found!";
0156             }
0157           } else {
0158             ss << "[SiStripFecCabling::" << __func__ << "]"
0159                << " CCU address " << conn.ccuAddr() << " not found!";
0160           }
0161         } else {
0162           ss << "[SiStripFecCabling::" << __func__ << "]"
0163              << " FEC ring " << conn.fecRing() << " not found!";
0164         }
0165       } else {
0166         ss << "[SiStripFecCabling::" << __func__ << "]"
0167            << " FEC slot " << conn.fecSlot() << " not found!";
0168       }
0169     } else {
0170       ss << "[SiStripFecCabling::" << __func__ << "]"
0171          << " FEC crate " << conn.fecCrate() << " not found!";
0172     }
0173 
0174     if (!ss.str().empty()) {
0175       edm::LogWarning(mlCabling_) << ss.str();
0176     }
0177     return nullptr;
0178   }
0179 }  // namespace
0180 
0181 const SiStripModule &SiStripFecCabling::module(const FedChannelConnection &conn) const {
0182   auto module = moduleFrom(crates(), conn);
0183   if (module) {
0184     return *module;
0185   }
0186 
0187   static const SiStripModule s_module{FedChannelConnection{}};
0188   return s_module;
0189 }
0190 
0191 SiStripModule *SiStripFecCabling::module(const FedChannelConnection &conn) { return moduleFrom(crates(), conn); }
0192 
0193 // -----------------------------------------------------------------------------
0194 //
0195 const SiStripModule &SiStripFecCabling::module(const uint32_t &dcu_id) const {
0196   for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
0197        ++icrate) {
0198     for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
0199       for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
0200            ++iring) {
0201         for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
0202              ++iccu) {
0203           for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
0204                ++imod) {
0205             if ((*imod).dcuId() == dcu_id) {
0206               return *imod;
0207             }
0208           }
0209         }
0210       }
0211     }
0212   }
0213   static const SiStripModule module{FedChannelConnection{}};
0214   return module;
0215 }
0216 
0217 // -----------------------------------------------------------------------------
0218 //
0219 NumberOfDevices SiStripFecCabling::countDevices() const {
0220   NumberOfDevices num_of_devices;  // simple container class used for counting
0221 
0222   std::vector<uint16_t> fed_crates;
0223   std::vector<uint16_t> fed_slots;
0224   std::vector<uint16_t> fed_ids;
0225   for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
0226        ++icrate) {
0227     for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
0228       for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
0229            ++iring) {
0230         for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
0231              ++iccu) {
0232           for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
0233                ++imod) {
0234             // APVs
0235             if (imod->activeApv(32)) {
0236               num_of_devices.nApvs_++;
0237             }
0238             if (imod->activeApv(33)) {
0239               num_of_devices.nApvs_++;
0240             }
0241             if (imod->activeApv(34)) {
0242               num_of_devices.nApvs_++;
0243             }
0244             if (imod->activeApv(35)) {
0245               num_of_devices.nApvs_++;
0246             }
0247             if (imod->activeApv(36)) {
0248               num_of_devices.nApvs_++;
0249             }
0250             if (imod->activeApv(37)) {
0251               num_of_devices.nApvs_++;
0252             }
0253             if (imod->dcuId()) {
0254               num_of_devices.nDcuIds_++;
0255             }
0256             if (imod->detId()) {
0257               num_of_devices.nDetIds_++;
0258             }
0259 
0260             // APV pairs
0261             num_of_devices.nApvPairs_ += imod->nApvPairs();
0262             if (imod->nApvPairs() == 0) {
0263               num_of_devices.nApvPairs0_++;
0264             } else if (imod->nApvPairs() == 1) {
0265               num_of_devices.nApvPairs1_++;
0266             } else if (imod->nApvPairs() == 2) {
0267               num_of_devices.nApvPairs2_++;
0268             } else if (imod->nApvPairs() == 3) {
0269               num_of_devices.nApvPairs3_++;
0270             } else {
0271               num_of_devices.nApvPairsX_++;
0272             }
0273 
0274             // FED crates, slots, ids, channels
0275             for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
0276               uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
0277               uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
0278               uint16_t fed_id = imod->fedCh(ipair).fedId_;
0279 
0280               if (fed_id) {
0281                 num_of_devices.nFedChans_++;
0282 
0283                 std::vector<uint16_t>::iterator icrate = find(fed_crates.begin(), fed_crates.end(), fed_crate);
0284                 if (icrate == fed_crates.end()) {
0285                   num_of_devices.nFedCrates_++;
0286                   fed_crates.push_back(fed_crate);
0287                 }
0288 
0289                 std::vector<uint16_t>::iterator islot = find(fed_slots.begin(), fed_slots.end(), fed_slot);
0290                 if (islot == fed_slots.end()) {
0291                   num_of_devices.nFedSlots_++;
0292                   fed_slots.push_back(fed_slot);
0293                 }
0294 
0295                 std::vector<uint16_t>::iterator ifed = find(fed_ids.begin(), fed_ids.end(), fed_id);
0296                 if (ifed == fed_ids.end()) {
0297                   num_of_devices.nFedIds_++;
0298                   fed_ids.push_back(fed_id);
0299                 }
0300               }
0301             }
0302 
0303             // FE devices
0304             if (imod->dcu()) {
0305               num_of_devices.nDcus_++;
0306             }
0307             if (imod->mux()) {
0308               num_of_devices.nMuxes_++;
0309             }
0310             if (imod->pll()) {
0311               num_of_devices.nPlls_++;
0312             }
0313             if (imod->lld()) {
0314               num_of_devices.nLlds_++;
0315             }
0316 
0317             // FE modules
0318             num_of_devices.nCcuChans_++;
0319           }
0320           num_of_devices.nCcuAddrs_++;
0321         }
0322         num_of_devices.nFecRings_++;
0323       }
0324       num_of_devices.nFecSlots_++;
0325     }
0326     num_of_devices.nFecCrates_++;
0327   }
0328 
0329   return num_of_devices;
0330 }
0331 
0332 // -----------------------------------------------------------------------------
0333 //
0334 void SiStripFecCabling::print(std::stringstream &ss) const {
0335   uint32_t valid = 0;
0336   uint32_t total = 0;
0337   ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
0338   ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
0339   for (std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate) {
0340     ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
0341     for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
0342       ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
0343       for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
0344            ++iring) {
0345         ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
0346         for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
0347              ++iccu) {
0348           ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr()
0349              << std::endl;
0350           for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
0351                ++imod) {
0352             SiStripModule::FedCabling conns = imod->fedChannels();
0353             SiStripModule::FedCabling::const_iterator ii = conns.begin();
0354             SiStripModule::FedCabling::const_iterator jj = conns.end();
0355             for (; ii != jj; ++ii) {
0356               if (ii->second.fedId_ != sistrip::invalid_ && ii->second.fedCh_ != sistrip::invalid_) {
0357                 valid++;
0358               }
0359               total++;
0360             }
0361             ss << *imod << std::endl;
0362           }
0363         }
0364       }
0365     }
0366   }
0367   ss << "Number of connected:   " << valid << std::endl << "Number of connections: " << total << std::endl;
0368 }
0369 
0370 // -----------------------------------------------------------------------------
0371 //
0372 void SiStripFecCabling::terse(std::stringstream &ss) const {
0373   ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
0374   for (std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate) {
0375     for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
0376       for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
0377            ++iring) {
0378         for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
0379              ++iccu) {
0380           for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
0381                ++imod) {
0382             imod->terse(ss);
0383             ss << std::endl;
0384           }
0385         }
0386       }
0387     }
0388   }
0389 }
0390 
0391 // -----------------------------------------------------------------------------
0392 //
0393 std::ostream &operator<<(std::ostream &os, const SiStripFecCabling &cabling) {
0394   std::stringstream ss;
0395   cabling.print(ss);
0396   os << ss.str();
0397   return os;
0398 }