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File indexing completed on 2021-02-14 12:51:31

0001 #ifndef CondFormats_SiPixelObjects_interface_SiPixelROCsStatusAndMapping_h
0002 #define CondFormats_SiPixelObjects_interface_SiPixelROCsStatusAndMapping_h
0003 
0004 namespace pixelgpudetails {
0005   // Maximum fed for phase1 is 150 but not all of them are filled
0006   // Update the number FED based on maximum fed found in the cabling map
0007   constexpr unsigned int MAX_FED = 150;
0008   constexpr unsigned int MAX_LINK = 48;  // maximum links/channels for Phase 1
0009   constexpr unsigned int MAX_ROC = 8;
0010   constexpr unsigned int MAX_SIZE = MAX_FED * MAX_LINK * MAX_ROC;
0011   constexpr unsigned int MAX_SIZE_BYTE_BOOL = MAX_SIZE * sizeof(unsigned char);
0012 }  // namespace pixelgpudetails
0013 
0014 struct SiPixelROCsStatusAndMapping {
0015   alignas(128) unsigned int fed[pixelgpudetails::MAX_SIZE];
0016   alignas(128) unsigned int link[pixelgpudetails::MAX_SIZE];
0017   alignas(128) unsigned int roc[pixelgpudetails::MAX_SIZE];
0018   alignas(128) unsigned int rawId[pixelgpudetails::MAX_SIZE];
0019   alignas(128) unsigned int rocInDet[pixelgpudetails::MAX_SIZE];
0020   alignas(128) unsigned int moduleId[pixelgpudetails::MAX_SIZE];
0021   alignas(128) unsigned char badRocs[pixelgpudetails::MAX_SIZE];
0022   alignas(128) unsigned int size = 0;
0023 };
0024 
0025 #endif  // CondFormats_SiPixelObjects_interface_SiPixelROCsStatusAndMapping_h