File indexing completed on 2024-04-06 12:06:57
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0019 #include "CSCDQM_EventProcessor.h"
0020
0021 namespace cscdqm {
0022
0023
0024
0025
0026 void EventProcessor::updateEfficiencyHistos() {
0027 MonitorObject *me = nullptr, *me1 = nullptr;
0028
0029 if (config->getNEvents() > 0) {
0030 if (getEMUHisto(h::EMU_CSC_REPORTING, me)) {
0031 const TH2* rep = dynamic_cast<const TH2*>(me->getTH1());
0032
0033
0034 const TObject* tobj = me->getRefRootObject();
0035
0036
0037
0038
0039 if (tobj) {
0040 const TH2* ref = dynamic_cast<const TH2*>(tobj);
0041 summary.ReadReportingChambersRef(rep,
0042 ref,
0043 config->getEFF_COLD_THRESHOLD(),
0044 config->getEFF_COLD_SIGFAIL(),
0045 config->getEFF_HOT_THRESHOLD(),
0046 config->getEFF_HOT_SIGFAIL());
0047 } else {
0048 summary.ReadReportingChambers(rep, 1.0);
0049 }
0050
0051 if (getEMUHisto(h::EMU_CSC_FORMAT_ERRORS, me1)) {
0052 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0053 summary.ReadErrorChambers(rep, err, FORMAT_ERR, config->getEFF_ERR_THRESHOLD(), config->getEFF_ERR_SIGFAIL());
0054 }
0055
0056 if (getEMUHisto(h::EMU_CSC_L1A_OUT_OF_SYNC, me1)) {
0057 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0058 summary.ReadErrorChambers(rep, err, L1SYNC_ERR, config->getEFF_ERR_THRESHOLD(), config->getEFF_ERR_SIGFAIL());
0059 }
0060
0061 if (getEMUHisto(h::EMU_CSC_DMB_INPUT_FIFO_FULL, me1)) {
0062 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0063 summary.ReadErrorChambers(
0064 rep, err, FIFOFULL_ERR, config->getEFF_ERR_THRESHOLD(), config->getEFF_ERR_SIGFAIL());
0065 }
0066
0067 if (getEMUHisto(h::EMU_CSC_DMB_INPUT_TIMEOUT, me1)) {
0068 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0069 summary.ReadErrorChambers(
0070 rep, err, INPUTTO_ERR, config->getEFF_ERR_THRESHOLD(), config->getEFF_ERR_SIGFAIL());
0071 }
0072
0073 if (getEMUHisto(h::EMU_CSC_WO_ALCT, me1)) {
0074 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0075 summary.ReadErrorChambers(
0076 rep, err, NODATA_ALCT, config->getEFF_NODATA_THRESHOLD(), config->getEFF_NODATA_SIGFAIL());
0077 }
0078
0079 if (getEMUHisto(h::EMU_CSC_WO_CLCT, me1)) {
0080 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0081 summary.ReadErrorChambers(
0082 rep, err, NODATA_CLCT, config->getEFF_NODATA_THRESHOLD(), config->getEFF_NODATA_SIGFAIL());
0083 }
0084
0085 if (getEMUHisto(h::EMU_CSC_WO_CFEB, me1)) {
0086 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0087 summary.ReadErrorChambers(
0088 rep, err, NODATA_CFEB, config->getEFF_NODATA_THRESHOLD(), config->getEFF_NODATA_SIGFAIL());
0089 }
0090
0091 if (getEMUHisto(h::EMU_CSC_FORMAT_WARNINGS, me1)) {
0092 const TH2* err = dynamic_cast<const TH2*>(me1->getTH1());
0093 summary.ReadErrorChambers(
0094 rep, err, CFEB_BWORDS, config->getEFF_NODATA_THRESHOLD(), config->getEFF_NODATA_SIGFAIL());
0095 }
0096 }
0097
0098 writeShifterHistograms();
0099
0100
0101
0102
0103
0104 if (getEMUHisto(h::EMU_PHYSICS_ME1, me)) {
0105 LockType lock(me->mutex);
0106 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0107 summary.Write(tmp, 1);
0108 }
0109
0110 if (getEMUHisto(h::EMU_PHYSICS_ME2, me)) {
0111 LockType lock(me->mutex);
0112 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0113 summary.Write(tmp, 2);
0114 }
0115
0116 if (getEMUHisto(h::EMU_PHYSICS_ME3, me)) {
0117 LockType lock(me->mutex);
0118 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0119 summary.Write(tmp, 3);
0120 }
0121
0122 if (getEMUHisto(h::EMU_PHYSICS_ME4, me)) {
0123 LockType lock(me->mutex);
0124 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0125 summary.Write(tmp, 4);
0126 }
0127
0128 if (getEMUHisto(h::EMU_PHYSICS_EMU, me)) {
0129 LockType lock(me->mutex);
0130 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0131 summary.WriteMap(tmp);
0132 }
0133 }
0134
0135
0136
0137
0138
0139 if (config->getPROCESS_EFF_PARAMETERS()) {
0140 {
0141
0142 Address adr;
0143 bzero(&adr, sizeof(Address));
0144 adr.mask.side = adr.mask.station = adr.mask.ring = true;
0145 adr.mask.chamber = adr.mask.layer = adr.mask.cfeb = adr.mask.hv = false;
0146
0147 double e_detector = 0.0, e_side = 0.0, e_station = 0.0, e_ring = 0.0;
0148 uint32_t e_detector_ch = 0, e_side_ch = 0, e_station_ch = 0;
0149
0150 const HistoId parameters[] = {h::PAR_CSC_SIDEPLUS_STATION01_RING01, h::PAR_CSC_SIDEPLUS_STATION01_RING02,
0151 h::PAR_CSC_SIDEPLUS_STATION01_RING03, h::PAR_CSC_SIDEPLUS_STATION01,
0152 h::PAR_CSC_SIDEPLUS_STATION02_RING01, h::PAR_CSC_SIDEPLUS_STATION02_RING02,
0153 h::PAR_CSC_SIDEPLUS_STATION02, h::PAR_CSC_SIDEPLUS_STATION03_RING01,
0154 h::PAR_CSC_SIDEPLUS_STATION03_RING02, h::PAR_CSC_SIDEPLUS_STATION03,
0155 h::PAR_CSC_SIDEPLUS_STATION04_RING01, h::PAR_CSC_SIDEPLUS_STATION04_RING02,
0156 h::PAR_CSC_SIDEPLUS_STATION04, h::PAR_CSC_SIDEPLUS,
0157 h::PAR_CSC_SIDEMINUS_STATION01_RING01, h::PAR_CSC_SIDEMINUS_STATION01_RING02,
0158 h::PAR_CSC_SIDEMINUS_STATION01_RING03, h::PAR_CSC_SIDEMINUS_STATION01,
0159 h::PAR_CSC_SIDEMINUS_STATION02_RING01, h::PAR_CSC_SIDEMINUS_STATION02_RING02,
0160 h::PAR_CSC_SIDEMINUS_STATION02, h::PAR_CSC_SIDEMINUS_STATION03_RING01,
0161 h::PAR_CSC_SIDEMINUS_STATION03_RING02, h::PAR_CSC_SIDEMINUS_STATION03,
0162 h::PAR_CSC_SIDEMINUS_STATION04_RING01, h::PAR_CSC_SIDEMINUS_STATION04_RING02,
0163 h::PAR_CSC_SIDEMINUS_STATION04, h::PAR_CSC_SIDEMINUS};
0164
0165 bool calc = (config->getNEvents() > 0);
0166
0167 if (!calc) {
0168 e_detector = e_side = e_station = e_ring = -1.0;
0169 }
0170
0171 unsigned int parameter = 0;
0172 for (adr.side = 1; adr.side <= N_SIDES; adr.side++) {
0173 if (calc) {
0174 e_side = 0.0;
0175 e_side_ch = 0;
0176 }
0177
0178 adr.mask.station = true;
0179 for (adr.station = 1; adr.station <= N_STATIONS; adr.station++) {
0180 if (calc) {
0181 e_station = 0.0;
0182 e_station_ch = 0;
0183 }
0184
0185 adr.mask.ring = true;
0186 for (adr.ring = 1; adr.ring <= summary.getDetector().NumberOfRings(adr.station); adr.ring++) {
0187 if (calc) {
0188 e_ring = summary.GetEfficiencyHW(adr);
0189 uint32_t ch = summary.getDetector().NumberOfChambers(adr.station, adr.ring);
0190 e_station += (e_ring * ch);
0191 e_station_ch += ch;
0192 }
0193
0194 if (summary.getDetector().NumberOfRings(adr.station) > 1) {
0195 if (getParHisto(parameters[parameter++], me))
0196 me->Fill(e_ring);
0197 }
0198 }
0199
0200 adr.mask.ring = false;
0201 if (calc) {
0202 e_side += e_station;
0203 e_side_ch += e_station_ch;
0204 e_station = e_station / e_station_ch;
0205 }
0206
0207 if (getParHisto(parameters[parameter++], me))
0208 me->Fill(e_station);
0209 }
0210
0211 adr.mask.station = false;
0212 if (calc) {
0213 e_detector += e_side;
0214 e_detector_ch += e_side_ch;
0215 e_side = e_side / e_side_ch;
0216 }
0217
0218 if (getParHisto(parameters[parameter++], me))
0219 me->Fill(e_side);
0220 }
0221
0222 if (calc) {
0223 e_detector = e_detector / e_detector_ch;
0224 }
0225
0226 if (getParHisto(h::PAR_REPORT_SUMMARY, me))
0227 me->Fill(e_detector);
0228 }
0229 }
0230 }
0231
0232 void EventProcessor::writeShifterHistograms() {
0233 MonitorObject* me = nullptr;
0234
0235
0236 const int COLOR_GREEN = 1;
0237 const int COLOR_RED = 2;
0238 const int COLOR_BLUE = 3;
0239 const int COLOR_GREY = 4;
0240 const int COLOR_STANDBY = 5;
0241
0242 if (getEMUHisto(h::EMU_CSC_STATS_SUMMARY, me)) {
0243 LockType lock(me->mutex);
0244 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0245 if (!config->getIN_FULL_STANDBY()) {
0246 summary.WriteChamberState(tmp, 0x1, COLOR_GREEN, true, false);
0247 summary.WriteChamberState(tmp, HWSTATUSERRORBITS, COLOR_RED, false, true);
0248 }
0249 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0250 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false);
0251 }
0252
0253 if (getEMUHisto(h::EMU_CSC_STATS_OCCUPANCY, me)) {
0254 LockType lock(me->mutex);
0255 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0256 if (!config->getIN_FULL_STANDBY()) {
0257 summary.WriteChamberState(tmp, 0x4, COLOR_RED, true, false);
0258 summary.WriteChamberState(tmp, 0x8, COLOR_BLUE, false, false);
0259 }
0260 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0261 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0262 }
0263
0264 if (getEMUHisto(h::EMU_CSC_STATS_FORMAT_ERR, me)) {
0265 LockType lock(me->mutex);
0266 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0267 if (!config->getIN_FULL_STANDBY()) {
0268 summary.WriteChamberState(tmp, 0x10, COLOR_RED, true, false);
0269 }
0270 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0271 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0272 }
0273
0274 if (getEMUHisto(h::EMU_CSC_STATS_L1SYNC_ERR, me)) {
0275 LockType lock(me->mutex);
0276 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0277 if (!config->getIN_FULL_STANDBY()) {
0278 summary.WriteChamberState(tmp, 0x20, COLOR_RED, true, false);
0279 }
0280 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0281 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0282 }
0283
0284 if (getEMUHisto(h::EMU_CSC_STATS_FIFOFULL_ERR, me)) {
0285 LockType lock(me->mutex);
0286 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0287 if (!config->getIN_FULL_STANDBY()) {
0288 summary.WriteChamberState(tmp, 0x40, COLOR_RED, true, false);
0289 }
0290 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0291 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0292 }
0293
0294 if (getEMUHisto(h::EMU_CSC_STATS_INPUTTO_ERR, me)) {
0295 LockType lock(me->mutex);
0296 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0297 if (!config->getIN_FULL_STANDBY()) {
0298 summary.WriteChamberState(tmp, 0x80, COLOR_RED, true, false);
0299 }
0300 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0301 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0302 }
0303
0304 if (getEMUHisto(h::EMU_CSC_STATS_WO_ALCT, me)) {
0305 LockType lock(me->mutex);
0306 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0307 if (!config->getIN_FULL_STANDBY()) {
0308 summary.WriteChamberState(tmp, 0x100, COLOR_RED, true, false);
0309 }
0310 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0311 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0312 }
0313
0314 if (getEMUHisto(h::EMU_CSC_STATS_WO_CLCT, me)) {
0315 LockType lock(me->mutex);
0316 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0317 if (!config->getIN_FULL_STANDBY()) {
0318 summary.WriteChamberState(tmp, 0x200, COLOR_RED, true, false);
0319 }
0320 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0321 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0322 }
0323
0324 if (getEMUHisto(h::EMU_CSC_STATS_WO_CFEB, me)) {
0325 LockType lock(me->mutex);
0326 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0327 if (!config->getIN_FULL_STANDBY()) {
0328 summary.WriteChamberState(tmp, 0x400, COLOR_RED, true, false);
0329 }
0330 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0331 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0332 }
0333
0334 if (getEMUHisto(h::EMU_CSC_STATS_CFEB_BWORDS, me)) {
0335 LockType lock(me->mutex);
0336 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0337 if (!config->getIN_FULL_STANDBY()) {
0338 summary.WriteChamberState(tmp, 0x800, COLOR_RED, true, false);
0339 }
0340 summary.WriteChamberState(tmp, 0x1000, COLOR_STANDBY, false);
0341 summary.WriteChamberState(tmp, 0x2, COLOR_GREY, false, false);
0342 }
0343 }
0344
0345
0346
0347
0348
0349 void EventProcessor::standbyEfficiencyHistos(HWStandbyType& standby) {
0350 Address adr;
0351 bzero(&adr, sizeof(Address));
0352 adr.mask.side = true;
0353 adr.mask.station = adr.mask.ring = adr.mask.chamber = adr.mask.layer = adr.mask.cfeb = adr.mask.hv = false;
0354
0355 adr.side = 1;
0356 summary.SetValue(adr, STANDBY, (standby.MeP ? 1 : 0));
0357 if (!standby.MeP) {
0358 summary.SetValue(adr, WAS_ON);
0359 }
0360
0361 adr.side = 2;
0362 summary.SetValue(adr, STANDBY, (standby.MeM ? 1 : 0));
0363 if (!standby.MeM) {
0364 summary.SetValue(adr, WAS_ON);
0365 }
0366
0367 MonitorObject* me = nullptr;
0368 if (getEMUHisto(h::EMU_CSC_STANDBY, me)) {
0369 LockType lock(me->mutex);
0370 TH2* tmp = dynamic_cast<TH2*>(me->getTH1Lock());
0371
0372
0373 summary.WriteChamberState(tmp, 0x1000, 5);
0374
0375
0376 summary.WriteChamberState(tmp, 0x3000, 1, false);
0377 }
0378 }
0379
0380 }