Back to home page

Project CMSSW displayed by LXR

 
 

    


File indexing completed on 2024-04-06 12:08:28

0001 #ifndef DQM_SiStripCommissioningAnalysis_FedCablingAlgorithm_H
0002 #define DQM_SiStripCommissioningAnalysis_FedCablingAlgorithm_H
0003 
0004 #include "FWCore/ParameterSet/interface/ParameterSet.h"
0005 #include "DQM/SiStripCommissioningAnalysis/interface/CommissioningAlgorithm.h"
0006 #include <vector>
0007 
0008 class FedCablingAnalysis;
0009 class TH1;
0010 
0011 /** 
0012    @class FedCablingAlgorithm
0013    @author R.Bainbridge
0014    @brief Histogram-based analysis for connection loop.
0015 */
0016 class FedCablingAlgorithm : public CommissioningAlgorithm {
0017 public:
0018   // ---------- Con(de)structors and typedefs ----------
0019 
0020   FedCablingAlgorithm(const edm::ParameterSet& pset, FedCablingAnalysis* const);
0021 
0022   ~FedCablingAlgorithm() override { ; }
0023 
0024   /** Pointer to FED id histogram. */
0025   inline const Histo& hFedId() const;
0026 
0027   /** Pointer to FED channel histogram. */
0028   inline const Histo& hFedCh() const;
0029 
0030 private:
0031   FedCablingAlgorithm() { ; }
0032 
0033   /** Extracts and organises histograms. */
0034   void extract(const std::vector<TH1*>&) override;
0035 
0036   /** Performs histogram anaysis. */
0037   void analyse() override;
0038 
0039 private:
0040   /** Histo containing FED id */
0041   Histo hFedId_;
0042 
0043   /** Histo containing FED channel */
0044   Histo hFedCh_;
0045 };
0046 
0047 const FedCablingAlgorithm::Histo& FedCablingAlgorithm::hFedId() const { return hFedId_; }
0048 const FedCablingAlgorithm::Histo& FedCablingAlgorithm::hFedCh() const { return hFedCh_; }
0049 
0050 #endif  // DQM_SiStripCommissioningAnalysis_FedCablingAlgorithm_H