Back to home page

Project CMSSW displayed by LXR

 
 

    


File indexing completed on 2021-02-14 13:11:40

0001 #include "DQM/SiStripCommissioningSummary/interface/FedCablingSummaryFactory.h"
0002 #include "DQM/SiStripCommissioningSummary/interface/SummaryGenerator.h"
0003 #include "DataFormats/SiStripCommon/interface/SiStripEnumsAndStrings.h"
0004 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0005 #include <iostream>
0006 #include <sstream>
0007 
0008 using namespace sistrip;
0009 
0010 // -----------------------------------------------------------------------------
0011 //
0012 uint32_t SummaryPlotFactory<FedCablingAnalysis*>::init(const sistrip::Monitorable& mon,
0013                                                        const sistrip::Presentation& pres,
0014                                                        const sistrip::View& view,
0015                                                        const std::string& level,
0016                                                        const sistrip::Granularity& gran,
0017                                                        const std::map<uint32_t, FedCablingAnalysis*>& data) {
0018   // Some initialisation
0019   SummaryPlotFactoryBase::init(mon, pres, view, level, gran);
0020 
0021   // Check if generator class exists
0022   if (!SummaryPlotFactoryBase::generator_) {
0023     return 0;
0024   }
0025 
0026   // Extract monitorable
0027   std::map<uint32_t, FedCablingAnalysis*>::const_iterator iter = data.begin();
0028   for (; iter != data.end(); iter++) {
0029     float value = static_cast<float>(sistrip::invalid_);
0030     if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_ID) {
0031       value = iter->second->fedId();
0032     } else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_CH) {
0033       value = iter->second->fedCh();
0034     } else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_ADC_LEVEL) {
0035       value = iter->second->adcLevel();
0036     } else {
0037       edm::LogWarning(mlSummaryPlots_) << "[SummaryPlotFactory::" << __func__ << "]"
0038                                        << " Unexpected monitorable: "
0039                                        << SiStripEnumsAndStrings::monitorable(SummaryPlotFactoryBase::mon_);
0040       continue;
0041     }
0042     SummaryPlotFactoryBase::generator_->fillMap(
0043         SummaryPlotFactoryBase::level_, SummaryPlotFactoryBase::gran_, iter->first, value);
0044   }
0045 
0046   return SummaryPlotFactoryBase::generator_->nBins();
0047 }
0048 
0049 //------------------------------------------------------------------------------
0050 //
0051 void SummaryPlotFactory<FedCablingAnalysis*>::fill(TH1& summary_histo) {
0052   // Histogram filling and formating
0053   SummaryPlotFactoryBase::fill(summary_histo);
0054 
0055   if (!SummaryPlotFactoryBase::generator_) {
0056     return;
0057   }
0058 
0059   // Histogram formatting
0060   if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_ID) {
0061     SummaryPlotFactoryBase::generator_->axisLabel("FED id");
0062   } else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_FED_CH) {
0063     SummaryPlotFactoryBase::generator_->axisLabel("FED channel");
0064   } else if (SummaryPlotFactoryBase::mon_ == sistrip::FED_CABLING_ADC_LEVEL) {
0065     SummaryPlotFactoryBase::generator_->axisLabel("Signal level [ADC]");
0066   } else {
0067     edm::LogWarning(mlSummaryPlots_) << "[SummaryPlotFactory::" << __func__ << "]"
0068                                      << " Unexpected SummaryHisto value:"
0069                                      << SiStripEnumsAndStrings::monitorable(SummaryPlotFactoryBase::mon_);
0070   }
0071 }