SiStripCommissioningSummary/src/ViewTranslator.cc

0001 #include "DQM/SiStripCommissioningSummary/interface/ViewTranslator.h"
0002 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
0003 #include "DataFormats/SiStripCommon/interface/SiStripFecKey.h"
0004 #include "DataFormats/SiStripCommon/interface/SiStripFedKey.h"
0005 #include "DataFormats/SiStripCommon/interface/SiStripDetKey.h"
0006 #include "DataFormats/SiStripDetId/interface/SiStripDetId.h"
0007 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0008 #include <iostream>
0009 #include <sstream>
0010 #include <fstream>
0011
0012 using namespace sistrip;
0013
0014 // -----------------------------------------------------------------------------
0015 //
0016 void ViewTranslator::buildMaps(const SiStripFedCabling& cabling, Mapping& det_to_fec, Mapping& fed_to_fec) {
0017   //   if ( !cabling ) {
0018   //     edm::LogWarning(mlCabling_)
0019   //       << "[ViewTranslator::" << __func__ << "]"
0020   //       << " NULL pointer to FED cabling object!";
0021   //     return;
0022   //   }
0023
0024   // Iterator through cabling, construct keys and push back into std::map
0025   for (auto ifed = cabling.fedIds().begin(); ifed != cabling.fedIds().end(); ++ifed) {
0026     auto conns = cabling.fedConnections(*ifed);
0027     for (auto ichan = conns.begin(); ichan != conns.end(); ichan++) {
0028       if (ichan->fedId()) {
0029         uint32_t fed =
0030             SiStripFedKey(*ifed, SiStripFedKey::feUnit(ichan->fedCh()), SiStripFedKey::feChan(ichan->fedCh())).key();
0031
0032         uint32_t fec = SiStripFecKey(ichan->fecCrate(),
0033                                      ichan->fecSlot(),
0034                                      ichan->fecRing(),
0035                                      ichan->ccuAddr(),
0036                                      ichan->ccuChan(),
0037                                      ichan->lldChannel())
0038                            .key();
0039
0040         SiStripDetId det_id(ichan->detId(), ichan->apvPairNumber());
0041         uint32_t det = SiStripDetKey(det_id).key();
0042
0043         det_to_fec[det] = fec;
0044         fed_to_fec[fed] = fec;
0045       }
0046     }
0047   }
0048
0049   LogTrace(mlCabling_) << "[ViewTranslator::" << __func__ << "]"
0050                        << " Size of FedToFec std::map: " << fed_to_fec.size()
0051                        << ", size of DetToFec std::map: " << det_to_fec.size();
0052 }
0053
0054 // -----------------------------------------------------------------------------
0055 //
0056 uint32_t ViewTranslator::fedToFec(const uint32_t& fed_key_mask, const Mapping& input, Mapping& output) {
0057   if (input.empty()) {
0058     edm::LogWarning(mlCabling_) << "[ViewTranslator::" << __func__ << "]"
0059                                 << " Input std::map is empty!";
0060     return 0;
0061   }
0062
0063   //   Mapping::iterator iter;
0064   //   SiStripFedKey fed_key( fed_key_mask );
0065
0066   //   if( fed_key.detId() == sistrip::invalid_ ||
0067   //       fed_key.apvPair() == sistrip::invalid_ ) {
0068   //     edm::LogWarning(mlCabling_)
0069   //       << "[ViewTranslator::" << __func__ << "]"
0070   //       << " DetKey is not defined!";
0071   //     output = input;
0072   //     return output.size();
0073   //   }
0074
0075   //   if( fed_key.detId() != sistrip::invalid_ &&
0076   //       fed_key.apvPair() != sistrip::invalid_ ) {
0077   //     iter=input->find( fed_key_mask );
0078   //     output[ (*iter).first ] = (*iter).second;
0079   //     LogTrace(mlSummaryPlots_) << "both are not masked";
0080   //   }
0081
0082   //   if( fed_key.detId()!=0xFFFFFFFF && fed_key.apvPair()==0xFFFF ) {
0083   //     LogTrace(mlSummaryPlots_) << "apv is masked";
0084   //     for(iter=input->begin() ; iter!=input->end() ; iter++) {
0085   //       DetKey = SiStripFedKey( (*iter).first );
0086   //       if(fed_key.detId()==DetKey.detId())
0087   //    output[ (*iter).first ]=( (*iter).second );
0088   //     } //for(iter=input->begin() ; iter!=input->end() ; iter++)
0089   //   }//if( fed_key.detId_!=0xFFFFFFFF && fed_key.apvPair_==0xFFFF )
0090   //   else LogTrace(mlSummaryPlots_) << "Cannot find the det to fec std::map in the root file. ";
0091
0092   return 0;
0093 }
0094
0095 // -----------------------------------------------------------------------------
0096 //
0097 uint32_t ViewTranslator::detToFec(const uint32_t& det_key_mask, const Mapping& input, Mapping& output) {
0098   //   if( input.empty() ) {
0099   //     edm::LogWarning(mlCabling_)
0100   //       << "[ViewTranslator::" << __func__ << "]"
0101   //       << " Input std::map is empty!";
0102   //     return 0 ;
0103   //   }
0104
0105   //   Mapping::iterator iter;
0106   //   SiStripDetKey::Path det_key = SiStripDetKey::path( det_key_mask );
0107
0108   //   if( det_key.detId_ == sistrip::invalid_ ||
0109   //       det_key.apvPair_ == sistrip::invalid_ ) {
0110   //     edm::LogWarning(mlCabling_)
0111   //       << "[ViewTranslator::" << __func__ << "]"
0112   //       << " DetKey is not defined!";
0113   //     output = input;
0114   //     return output.size();
0115   //   }
0116
0117   //   if( det_key.detId_ != sistrip::invalid_ &&
0118   //       det_key.apvPair_ != sistrip::invalid_ ) {
0119   //     iter=input->find( det_key_mask );
0120   //     output[ (*iter).first ] = (*iter).second;
0121   //     LogTrace(mlSummaryPlots_) << "both are not masked";
0122   //   }
0123
0124   //   if( det_key.detId_!=0xFFFFFFFF && det_key.apvPair_==0xFFFF ) {
0125   //     LogTrace(mlSummaryPlots_) << "apv is masked";
0126   //     for(iter=input->begin() ; iter!=input->end() ; iter++) {
0127   //       DetKey = SiStripDetKey::path( (*iter).first );
0128   //       if(det_key.detId_==DetKey.detId_)
0129   //    output[ (*iter).first ]=( (*iter).second );
0130   //     } //for(iter=input->begin() ; iter!=input->end() ; iter++)
0131   //   }//if( det_key.detId_!=0xFFFFFFFF && det_key.apvPair_==0xFFFF )
0132   //   else LogTrace(mlSummaryPlots_) << "Cannot find the det to fec std::map in the root file. ";
0133
0134   return 0;  //@@ temp!
0135 }
0136
0137 // -----------------------------------------------------------------------------
0138 //
0139 // void ViewTranslator::fedToFec( const uint32_t& fed_key_mask,
0140 //                 const Mapping& input,
0141 //                 Mapping& output ) {
0142
0143 //       Mapping::iterator iter;
0144 //       uint16_t fedId=0;   //fedId
0145 //       uint16_t feUnit=0;  //Front End Unit
0146 //       uint16_t feChan=0;   //Front End Channel
0147 //       uint16_t fedApv=0;
0148
0149 //       //unpack the FED key to tranlsate into the corresponding FEC key(s)
0150 //       SiStripFedKey::Path FedKey = SiStripFedKey::path(fed_key_mask);
0151 //       fedId=FedKey.fedId_;
0152 //       feUnit=FedKey.feUnit_;
0153 //       feChan=FedKey.feChan_;
0154 //       fedApv=FedKey.fedApv_;
0155
0156 //       if(fedId==0 && feUnit==0 && feChan==0 && fedApv == sistrip::invalid_ ) {
0157 //  output=*(input);
0158 //       }
0159
0160 //       if(fedId!=0 && feUnit!=0 && feChan!=0 && fedApv == sistrip::invalid_) {
0161 //           iter=input->find(fed_key_mask);
0162 //   output[fed_key_mask]=(*iter).second;
0163 //        }
0164
0165 //        if(fedId!=0 && feUnit!=0 && feChan==0 && fedApv == sistrip::invalid_ ) {
0166 //   for(iter=input->begin(); iter!=input->end(); iter++) {
0167 //     FedKey = SiStripFedKey::path( (*iter).first );
0168 //     if(fedId==FedKey.fedId_ && feUnit==FedKey.feUnit_) {
0169 //       output[ (*iter).first ] = (*iter).second;
0170 //     }// if
0171 //   }// for
0172 //        }// if
0173
0174 //        if(fedId!=0 && feUnit==0 && feChan==0) {
0175 //   for(iter=input->begin(); iter!=input->end(); iter++) {
0176 //     FedKey = SiStripFedKey::path( (*iter).first ); //FedKey is the key from the std::map
0177 //     if( fedId==FedKey.fedId_ ) {
0178 //       output[ (*iter).first ] = (*iter).second;
0179 //     } else LogTrace(mlSummaryPlots_) << "The fedId cannot be found. Please check readout path";
0180 //   } //for
0181 //        }//if
0182
0183 //     } else LogTrace(mlSummaryPlots_) << "The fed to fec std::map could not be found in the root file" << endl << "Please load the ViewTranslator module to create the requisite std::maps";
0184
0185 //     f->Close();
0186
0187 //   } //if(TFile::Open(fname.cstr())
0188 //   else LogTrace(mlSummaryPlots_) << "Error:Cannot open root file.";
0189
0190 // }
0191
0192 // -----------------------------------------------------------------------------
0193 //
0194 void ViewTranslator::writeMapsToFile(std::string fname, Mapping& det, Mapping& fed) {
0195   //   Mapping *det_to_fec;
0196   //   Mapping *fed_to_fec;
0197
0198   //   det_to_fec = &det;
0199   //   fed_to_fec = &fed;
0200
0201   //   if(TFile::Open(fname.c_str())!=NULL) {
0202   //     TFile *f=TFile::Open(fname.c_str(), "UPDATE");
0203   //     gDirectory->cd();
0204   //     TDirectory *std::mapdir = gDirectory;
0205   //     gDirectory->cd("/DQMData/SiStrip");
0206   //     std::mapdir=gDirectory;
0207   //     std::mapdir->WriteObject(det_to_fec, "det_to_fec");
0208   //     std::mapdir->WriteObject(fed_to_fec, "fed_to_fec");
0209   //     LogTrace(mlSummaryPlots_) << "Wrote the std::maps";
0210   //     f->Close();
0211   //   } else LogTrace(mlSummaryPlots_) << "Cannot find root file. Maps not written.";
0212 }