SiStripMonitorHardware/interface/SiStripSpyDigiConverter.h

0001 #ifndef DQM_SiStripMonitorHardware_SiStripSpyDigiConverter_H
0002 #define DQM_SiStripMonitorHardware_SiStripSpyDigiConverter_H
0003
0004 #include <memory>
0005 #include <vector>
0006
0007 #include "DataFormats/Common/interface/DetSetVector.h"
0008 #include "DataFormats/SiStripDigi/interface/SiStripRawDigi.h"
0009
0010 #include "DQM/SiStripMonitorHardware/interface/SiStripSpyUtilities.h"
0011 #include <cstdint>
0012
0013 // Forward define other classes
0014 class SiStripFedCabling;
0015
0016 namespace sistrip {
0017
0018   /*! \brief Converts scope mode like digis into virgin raw like digis by:
0019      *  -extracting the frame payload,
0020      *  -reordering to physical order and
0021      *  -merging the DetSets indexed by FedKey to DetSets indexed by DetId
0022      *
0023      *
0024      */
0025   class SpyDigiConverter {
0026   public:
0027     typedef edm::DetSetVector<SiStripRawDigi> DSVRawDigis;
0028
0029     //all methods are static so no instances are needed but allow anyway
0030     SpyDigiConverter() {}
0031     ~SpyDigiConverter() {}
0032
0033     /*! \brief Extract frames from the scope digis.
0034          *
0035          * If pAPVAddress is set, the map is filled with a map from FedKey to APVAddress.
0036          * minAllowedRange is the min allowed range of digis when determine the threshold.
0037          */
0038     static std::unique_ptr<DSVRawDigis> extractPayloadDigis(const DSVRawDigis* inputScopeDigis,
0039                                                             std::vector<uint32_t>* pAPVAddresses,
0040                                                             const bool discardDigisWithAPVAddrErr,
0041                                                             const sistrip::SpyUtilities::FrameQuality& aQuality,
0042                                                             const uint16_t expectedPos);
0043
0044     /* \brief Reorder from readout order to physical order */
0045     static std::unique_ptr<DSVRawDigis> reorderDigis(const DSVRawDigis* inputPayloadDigis);
0046
0047     /* \brief Merge channel digis into modules. */
0048     static std::unique_ptr<DSVRawDigis> mergeModuleChannels(const DSVRawDigis* inputPhysicalOrderChannelDigis,
0049                                                             const SiStripFedCabling& cabling);
0050
0051   private:
0052     typedef DSVRawDigis::detset DetSetRawDigis;
0053
0054     static void processFED(const uint16_t aPreviousFedId,
0055                            const bool discardDigisWithAPVAddrErr,
0056                            std::vector<uint32_t>* pAPVAddresses,
0057                            std::vector<DetSetRawDigis>& outputData,
0058                            std::vector<uint16_t>& aAddrVec,
0059                            std::vector<uint16_t>& aHeaderBitVec,
0060                            std::vector<uint16_t>& aTrailBitVec,
0061                            std::vector<DSVRawDigis::const_iterator>& aFedScopeDigis);
0062
0063   };  // end of SpyDigiConverter class.
0064
0065 }  // namespace sistrip
0066
0067 #endif  // DQM_SiStripMonitorHardware_SiStripSpyDigiConverter_H