Back to home page

Project CMSSW displayed by LXR

 
 

    


File indexing completed on 2021-07-13 03:15:45

0001 #ifndef DataFormats_CSCDigi_CSCConstants_h
0002 #define DataFormats_CSCDigi_CSCConstants_h
0003 
0004 /**
0005  * \class CSCConstants
0006  *
0007  * Static interface to basic chamber constants.
0008  */
0009 
0010 class CSCConstants {
0011 public:
0012   enum DDU_Info { NUM_DDUS = 5 };
0013 
0014   enum CFEB_Info {
0015     // Run-1: Maximum number of cathode front-end boards
0016     MAX_CFEBS_RUN1 = 5,
0017     // ME1/1 cases
0018     NUM_CFEBS_ME1A_GANGED = 1,
0019     NUM_CFEBS_ME1A_UNGANGED = 3,
0020     NUM_CFEBS_ME1B = 4,
0021     NUM_CFEBS_ME11_GANGED = NUM_CFEBS_ME1A_GANGED + NUM_CFEBS_ME1B,      // 5
0022     NUM_CFEBS_ME11_UNGANGED = NUM_CFEBS_ME1A_UNGANGED + NUM_CFEBS_ME1B,  // 7
0023     // Run-2: Maximum number of cathode front-end boards
0024     MAX_CFEBS_RUN2 = NUM_CFEBS_ME11_UNGANGED,  // 7
0025     // CFEBS for the rest of the system
0026     NUM_CFEBS_ME12 = 5,
0027     NUM_CFEBS_ME13 = 4,
0028     NUM_CFEBS_ME21 = 5,
0029     NUM_CFEBS_ME22 = 5,
0030     NUM_CFEBS_ME31 = 5,
0031     NUM_CFEBS_ME32 = 5,
0032     NUM_CFEBS_ME41 = 5,
0033     NUM_CFEBS_ME42 = 5
0034   };
0035 
0036   enum FPGA_Latency { CLCT_EMUL_TIME_OFFSET = 3, ALCT_EMUL_TIME_OFFSET = 6 };
0037 
0038   // Numbers obtained from https://twiki.cern.ch/twiki/pub/CMS/CSCDPGGeometry/table_of_csc_properties_150730.pdf
0039   enum WG_Info {
0040     NUM_WIREGROUPS_ME11 = 48,
0041     NUM_WIREGROUPS_ME12 = 64,
0042     NUM_WIREGROUPS_ME13 = 32,
0043     NUM_WIREGROUPS_ME21 = 112,
0044     NUM_WIREGROUPS_ME22 = 64,
0045     NUM_WIREGROUPS_ME31 = 96,
0046     NUM_WIREGROUPS_ME32 = 64,
0047     NUM_WIREGROUPS_ME41 = 96,
0048     NUM_WIREGROUPS_ME42 = 64,
0049     // this number should really be 112, but has always been 119 since the
0050     // CSC trigger was developed in 2006. Probably it would not hurt to change it to 112
0051     MAX_NUM_WIREGROUPS = 119,
0052     INVALID_WIREGROUP = 65535
0053   };
0054 
0055   // distrips, strips, half-strips
0056   enum Strip_Info {
0057     // Each CFEB reads out 8 distrips...
0058     NUM_DISTRIPS_PER_CFEB = 8,
0059     //...16 strips...
0060     NUM_STRIPS_PER_CFEB = 2 * NUM_DISTRIPS_PER_CFEB,
0061     //...32 half-strips.
0062     NUM_HALF_STRIPS_PER_CFEB = 2 * NUM_STRIPS_PER_CFEB,
0063     // There are exactly 80 or 112 strips...
0064     MAX_NUM_STRIPS_RUN1 = MAX_CFEBS_RUN1 * NUM_STRIPS_PER_CFEB,  // 80
0065     MAX_NUM_STRIPS_RUN2 = MAX_CFEBS_RUN2 * NUM_STRIPS_PER_CFEB,  // 112
0066     //...and 160 or 224 half-strips for 5 or 7 CFEBs...
0067     MAX_NUM_HALF_STRIPS_RUN1 = MAX_CFEBS_RUN1 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0068     MAX_NUM_HALF_STRIPS_RUN2 = MAX_CFEBS_RUN2 * NUM_HALF_STRIPS_PER_CFEB,  // 224
0069     // ...but depending on the chamber, there may or may not be strip staggering.
0070     /* CMS-MUO-16-001: "[..] alternate layers in a CSC are staggered by half a strip width, except
0071        in the ME1/1 chambers where the strips are narrower and the effect is small" */
0072     // _TRIGGER is added at the end, because these constants are only used in the trigger
0073     MAX_NUM_HALF_STRIPS_RUN1_TRIGGER = 1 + MAX_NUM_HALF_STRIPS_RUN1,  // 161
0074     MAX_NUM_HALF_STRIPS_RUN2_TRIGGER = 1 + MAX_NUM_HALF_STRIPS_RUN2,  // 225
0075     // Number of strips in ME11 (special case)
0076     NUM_STRIPS_ME1A_GANGED = NUM_CFEBS_ME1A_GANGED * NUM_STRIPS_PER_CFEB,      // 16
0077     NUM_STRIPS_ME1A_UNGANGED = NUM_CFEBS_ME1A_UNGANGED * NUM_STRIPS_PER_CFEB,  // 48
0078     NUM_STRIPS_ME1B = NUM_CFEBS_ME1B * NUM_STRIPS_PER_CFEB,                    // 64
0079     // Number of half-strips in ME11 (special case)
0080     NUM_HALF_STRIPS_ME1A_GANGED = NUM_CFEBS_ME1A_GANGED * NUM_HALF_STRIPS_PER_CFEB,      // 32
0081     NUM_HALF_STRIPS_ME1A_UNGANGED = NUM_CFEBS_ME1A_UNGANGED * NUM_HALF_STRIPS_PER_CFEB,  // 96
0082     NUM_HALF_STRIPS_ME1B = NUM_CFEBS_ME1B * NUM_HALF_STRIPS_PER_CFEB,                    // 128
0083     NUM_HALF_STRIPS_ME11_GANGED = NUM_CFEBS_ME11_GANGED * NUM_HALF_STRIPS_PER_CFEB,      // 160
0084     NUM_HALF_STRIPS_ME11_UNGANGED = NUM_CFEBS_ME11_UNGANGED * NUM_HALF_STRIPS_PER_CFEB,  // 224
0085     // max halfstrip number in ME1/1 chambers
0086     MAX_HALF_STRIP_ME1A_GANGED = NUM_HALF_STRIPS_ME1A_GANGED - 1,      // 31
0087     MAX_HALF_STRIP_ME1A_UNGANGED = NUM_HALF_STRIPS_ME1A_UNGANGED - 1,  // 95
0088     MAX_HALF_STRIP_ME1B = NUM_HALF_STRIPS_ME1B - 1,                    // 127
0089     // half-strips for the rest of the system
0090     NUM_HALF_STRIPS_ME12 = NUM_CFEBS_ME12 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0091     NUM_HALF_STRIPS_ME13 = NUM_CFEBS_ME13 * NUM_HALF_STRIPS_PER_CFEB,  // 128
0092     NUM_HALF_STRIPS_ME21 = NUM_CFEBS_ME21 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0093     NUM_HALF_STRIPS_ME22 = NUM_CFEBS_ME22 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0094     NUM_HALF_STRIPS_ME31 = NUM_CFEBS_ME31 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0095     NUM_HALF_STRIPS_ME32 = NUM_CFEBS_ME32 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0096     NUM_HALF_STRIPS_ME41 = NUM_CFEBS_ME41 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0097     NUM_HALF_STRIPS_ME42 = NUM_CFEBS_ME42 * NUM_HALF_STRIPS_PER_CFEB,  // 160
0098     // useful for the comparator code algorithm
0099     INVALID_HALF_STRIP = 65535
0100   };
0101 
0102   // CSCs have 6 layers. The key (reference) layer is the third layer
0103   enum Layer_Info { NUM_LAYERS = 6, KEY_CLCT_LAYER = 3, KEY_ALCT_LAYER = 3 };
0104 
0105   // Both ALCT and CLCTs have patterns. CLCTs have a better granularity than ALCTs, thus more patterns
0106   enum Pattern_Info {
0107     NUM_ALCT_PATTERNS = 3,
0108     ALCT_PATTERN_WIDTH = 5,
0109     ALCT_ACCELERATOR_PATTERN = 0,
0110     ALCT_COLLISIONA_PATTERN = 1,
0111     ALCT_COLLISIONB_PATTERN = 2,
0112     // Run-1 and Run-2 CSC trigger patterns
0113     NUM_CLCT_PATTERNS = 11,
0114     // Run-3 CSC trigger patterns
0115     NUM_CLCT_PATTERNS_RUN3 = 5,
0116     CLCT_PATTERN_WIDTH = 11,
0117     // Max number of wires participating in a pattern
0118     MAX_WIRES_IN_PATTERN = 14,
0119     NUM_COMPARATOR_CODES = 4096
0120   };
0121 
0122   enum Digis_Info { MAX_DIGIS_PER_ALCT = 10, MAX_DIGIS_PER_CLCT = 8 };
0123 
0124   enum LCT_stubs {
0125     // CSC local trigger considers 4-bit BX window (16 numbers) in the readout
0126     MAX_CLCT_TBINS = 16,
0127     MAX_ALCT_TBINS = 16,
0128     MAX_LCT_TBINS = 16,
0129     // Maximum allowed matching window size
0130     MAX_MATCH_WINDOW_SIZE = 7,
0131     // Each CLCT processor can send up to 2 CLCTs to TMB per BX
0132     MAX_CLCTS_PER_PROCESSOR = 2,
0133     MAX_CLCTS_READOUT = 2,
0134     // Each ALCT processor can send up to 2 ALCTs to TMB per BX
0135     MAX_ALCTS_PER_PROCESSOR = 2,
0136     MAX_ALCTS_READOUT = 2,
0137     // Each CSC can send up to 2 LCTs to the MPC per BX
0138     MAX_LCTS_PER_CSC = 2,
0139     // An MPC receives up to 18 LCTs from 9 CSCs in the trigger sector
0140     MAX_LCTS_PER_MPC = 18,
0141     /*
0142       An EMTF sector processor receives LCTs from 5 MPCS
0143       or 45 chambers when not considering overlapping EMTF SPs
0144       18 CSCs in ME1; 9 x 3 CSCs in ME2,3,4
0145     */
0146     MAX_CSCS_PER_EMTF_SP_NO_OVERLAP = 45,
0147     // Reference BX for LCTs in simulation and firmware
0148     LCT_CENTRAL_BX = 8,
0149     /*
0150       Reference BX for ALCTs in firmware. In the ALCT simulation,
0151       and in the motherboard simulation the ALCT central BX is 8.
0152       However, ALCT BX is shifted before they are inserted into the EDM
0153       ROOT file to have a central BX of 3 and be consistent with the firmware.
0154      */
0155     ALCT_CENTRAL_BX = 3,
0156     /*
0157       Reference BX for CLCTs in firmware. In the CLCT simulation, the central
0158       CLCT BX is 7. In the motherboard simulation they are shifted to 8 (in order
0159       to matched with ALCTs). But in the EDM ROOT file the CLCT central BX is 7
0160       to be consistent with the firmware.
0161      */
0162     CLCT_CENTRAL_BX = 7,
0163     // Offset between the ALCT and CLCT central BX in simulation
0164     ALCT_CLCT_OFFSET = 1
0165   };
0166 };
0167 
0168 #endif