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File indexing completed on 2021-02-14 13:14:43

0001 //_________________________________________________________
0002 //
0003 //  CSCTMBScope 9/11/03  B.Mohr
0004 //  Unpacks TMB Logic Analyzer and stores in CSCTMBScope.h
0005 //_________________________________________________________
0006 //
0007 #include "EventFilter/CSCRawToDigi/interface/CSCTMBScope.h"
0008 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0009 #include <iostream>
0010 
0011 #ifdef LOCAL_UNPACK
0012 bool CSCTMBScope::debug = false;
0013 #else
0014 std::atomic<bool> CSCTMBScope::debug{false};
0015 #endif
0016 
0017 CSCTMBScope::CSCTMBScope(const uint16_t *buf, int b05Line, int e05Line) {
0018   size_ = UnpackScope(buf, b05Line, e05Line);
0019 
0020 }  //CSCTMBScope
0021 
0022 int CSCTMBScope::UnpackScope(const uint16_t *buf, int b05Line, int e05Line) {
0023   int pretrig_chan[4] = {0, 0, 0, 0};
0024   unsigned int tbin_strt, tbin_stop;
0025   unsigned int ibit, jbit, itbin, ich, iram, iline, iadr;
0026   unsigned int lct_bxn;
0027 
0028   if (debug) {
0029     LogTrace("CSCTMBScope|CSCRawToDigi") << " .....TMBHeader -- unpacking Logic Analyzer......";
0030   }
0031 
0032   if ((e05Line - b05Line) == 1537) {
0033     if (debug)
0034       LogTrace("CSCTMBScope|CSCRawToDigi") << "Scope data found";
0035 
0036     //load scope_ram from raw-hits format readout
0037     iline = b05Line + 1;
0038     for (iram = 0; iram < 6; iram++) {
0039       for (iadr = 0; iadr < 256; iadr++) {
0040         itbin = iadr;  //ram_sel*256
0041         scope_ram[itbin][iram] = buf[iline];
0042         iline++;
0043       }
0044     }
0045 
0046     for (ich = 0; ich < 51; ich++)
0047       data[ich] = 0;  //clear all data
0048 
0049     //----- find pretrig chan offset -----------------
0050     pretrig_chan[0] = GetPretrig(0);
0051     pretrig_chan[1] = GetPretrig(32);
0052     pretrig_chan[2] = GetPretrig(48);
0053     pretrig_chan[3] = GetPretrig(64);
0054 
0055     //----- ram 1 ------------------------------------
0056     tbin_strt = pretrig_chan[0] - 7;
0057     tbin_stop = pretrig_chan[0] + 24;
0058 
0059     for (ich = 0; ich <= 14; ich++) {
0060       iram = ich / 16;
0061       jbit = 0;
0062       for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
0063         ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0064         data[ich] = (ibit << jbit) | data[ich];
0065         jbit++;
0066       }
0067     }
0068 
0069     //----- ram 2 ------------------------------------
0070     for (ich = 16; ich <= 30; ich++) {
0071       iram = ich / 16;
0072       jbit = 0;
0073       for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
0074         ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0075         data[ich - 1] = (ibit << jbit) | data[ich - 1];
0076         jbit++;
0077       }
0078     }
0079 
0080     //----- ram 3 ------------------------------------
0081     tbin_strt = pretrig_chan[1] - 7;
0082     tbin_stop = pretrig_chan[1] + 24;
0083 
0084     for (ich = 32; ich <= 36; ich++) {
0085       iram = ich / 16;
0086       jbit = 0;
0087       for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
0088         ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0089         data[ich - 2] = (ibit << jbit) | data[ich - 2];
0090         jbit++;
0091       }
0092     }
0093 
0094     tbin_strt = pretrig_chan[1] - 7 + 120;
0095     tbin_stop = pretrig_chan[1] + 24 + 120;
0096 
0097     for (ich = 37; ich <= 40; ich++) {
0098       iram = ich / 16;
0099       jbit = 0;
0100       for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
0101         ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0102         data[ich - 2] = (ibit << jbit) | data[ich - 2];
0103         jbit++;
0104       }
0105     }
0106 
0107     tbin_strt = pretrig_chan[1] - 7;
0108     tbin_stop = pretrig_chan[1] + 24;
0109 
0110     for (ich = 41; ich <= 46; ich++) {
0111       iram = ich / 16;
0112       jbit = 0;
0113       for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
0114         ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0115         data[ich - 2] = (ibit << jbit) | data[ich - 2];
0116         jbit++;
0117       }
0118     }
0119 
0120     //----- ram 4 ------------------------------------
0121     tbin_strt = pretrig_chan[2] - 7;
0122     tbin_stop = pretrig_chan[2] + 24;
0123 
0124     for (ich = 48; ich <= 53; ich++) {
0125       iram = ich / 16;
0126       jbit = 0;
0127       for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
0128         ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0129         data[ich - 3] = (ibit << jbit) | data[ich - 3];
0130         jbit++;
0131       }
0132     }
0133 
0134     //----- ram 5 - bxn ------------------------------
0135     lct_bxn = 0;
0136     jbit = 0;
0137 
0138     for (ich = 65; ich <= 76; ich++) {
0139       iram = ich / 16;
0140       itbin = pretrig_chan[3];
0141       ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0142       lct_bxn = (ibit << jbit) | lct_bxn;
0143       jbit++;
0144     }
0145     data[51] = lct_bxn;
0146 
0147     if (debug)
0148       LogTrace("CSCTMBScope|CSCRawToDigi") << "Scope bxn at LCT (seq_pretrig): " << lct_bxn;
0149 
0150     //----- now read back decoded scope data ---------
0151     if (debug) {
0152       for (ich = 0; ich <= 50; ich++) {
0153         for (itbin = 0; itbin < 32; itbin++) {
0154           ibit = (data[ich] >> itbin) & 1;
0155           if (ibit == 0)
0156             LogTrace("CSCTMBScope|CSCRawToDigi") << "_";  //display symbol for logic 0
0157           if (ibit == 1)
0158             LogTrace("CSCTMBScope|CSCRawToDigi") << "-";  //display symbol for logic 1
0159         }
0160       }
0161     }
0162 
0163   }  //end if(b05-e05)
0164 
0165   //-------------- if no scope data: fill everything with 0 --------------------
0166   else {
0167     for (ich = 0; ich < 51; ich++)
0168       data[ich] = 0;
0169     lct_bxn = 0xff0000;  //value not possible for real data (short)
0170     data[51] = lct_bxn;
0171 
0172     if (debug)
0173       LogTrace("CSCTMBScope|CSCRawToDigi") << "No scope data found: wrdcnt: " << (e05Line - b05Line);
0174   }
0175 
0176   if (debug) {
0177     LogTrace("CSCTMBScope|CSCRawToDigi") << " .....END -- unpacking Logic Analyzer...........";
0178   }
0179 
0180   return (e05Line - b05Line + 1);
0181 
0182 }  //UnpackScope
0183 
0184 int CSCTMBScope::GetPretrig(int ich) {
0185   unsigned int ibit, itbin, iram;
0186   int value = 0;
0187 
0188   ibit = 0;
0189   itbin = 0;
0190   iram = ich / 16;
0191   while (!ibit) {
0192     ibit = (scope_ram[itbin][iram] >> (ich % 16)) & 1;
0193     value = itbin;
0194     itbin++;
0195   }
0196 
0197   if (debug)
0198     LogTrace("CSCTMBScope|CSCRawToDigi") << "TMB SCOPE: ------- Pretrig value: " << value;
0199   return value;
0200 
0201 }  //GetPretrig