EcalRawToDigi/interface/DCCRawDataDefinitions.h

0001 #ifndef DCCRAWDATADEFINITIONS_
0002 #define DCCRAWDATADEFINITIONS_
0003
0004 enum globalFieds {
0005
0006   BLOCK_UNPACKED = 0,
0007   SKIP_BLOCK_UNPACKING = 1,
0008   STOP_EVENT_UNPACKING = 2,
0009
0010   B_MASK = 1,
0011   HEADERLENGTH = 9,
0012   HEADERSIZE = 72,
0013   EMPTYEVENTSIZE = 32,
0014
0015   PHYSICTRIGGER = 1,
0016   CALIBRATIONTRIGGER = 2,
0017   TESTTRIGGER = 3,
0018   TECHNICALTRIGGER = 4,
0019
0020   CH_ENABLED = 0,
0021   CH_DISABLED = 1,
0022   CH_TIMEOUT = 2,
0023   CH_HEADERERR = 3,
0024   CH_LINKERR = 5,
0025   CH_LENGTHERR = 6,
0026   CH_SUPPRESS = 7,
0027   CH_IFIFOFULL = 8,
0028   CH_L1AIFIFOFULL = 0xC,
0029   CH_FORCEDZS1 = 0xF,
0030
0031   SRP_NUMBFLAGS = 68,
0032   SRP_BLOCKLENGTH = 6,
0033   SRP_EB_NUMBFLAGS = 68,
0034
0035   BOEVALUE = 0x5,
0036   ERROR_EMPTYEVENT = 0x1,
0037   TOWERH_SIZE = 8,
0038   TRAILER_SIZE = 8,
0039   TCC_EB_NUMBTTS = 68,
0040   TCCID_SMID_SHIFT_EB = 27,
0041
0042   NUMB_SM = 54,
0043   NUMB_FE = 68,
0044   NUMB_TCC = 108,
0045   NUMB_XTAL = 5,
0046   NUMB_STRIP = 5,
0047   NUMB_PSEUDOSTRIPS = 30,   // input1 and input2 of TCC board has at most 30 PS_input (12 of which are duplicated)
0048   NUMB_TTS_TPG2_DUPL = 12,  //
0049   NUMB_TTS_TPG1 = 16,       // input1 of TCC board has at most 16 TP's
0050   NUMB_TTS_TPG2 = 12,       // input2 of TCC board has at most 12 TP's
0051
0052   NUMB_SM_EE_MIN_MIN = 1,
0053   NUMB_SM_EE_MIN_MAX = 9,
0054   NUMB_SM_EB_MIN_MIN = 10,
0055   NUMB_SM_EB_MIN_MAX = 27,
0056   NUMB_SM_EB_PLU_MIN = 28,
0057   NUMB_SM_EB_PLU_MAX = 45,
0058   NUMB_SM_EE_PLU_MIN = 46,
0059   NUMB_SM_EE_PLU_MAX = 54,
0060
0061   // two DCC have a missing interval in the CCU_id's
0062   SECTOR_EEM_CCU_JUMP = 8,
0063   SECTOR_EEP_CCU_JUMP = 53,
0064   MIN_CCUID_JUMP = 18,
0065   MAX_CCUID_JUMP = 24,
0066
0067   NUMB_TCC_EE_MIN_EXT_MIN = 19,  // outer TCC's in EE-
0068   NUMB_TCC_EE_MIN_EXT_MAX = 36,
0069   NUMB_TCC_EE_PLU_EXT_MIN = 73,  // outer TCC's in EE+
0070   NUMB_TCC_EE_PLU_EXT_MAX = 90
0071
0072 };
0073
0074 enum headerFields {
0075
0076   H_FEDID_B = 8,
0077   H_FEDID_MASK = 0xFFF,
0078
0079   H_BX_B = 20,
0080   H_BX_MASK = 0xFFF,
0081
0082   H_L1_B = 32,
0083   H_L1_MASK = 0xFFFFFF,
0084
0085   H_TTYPE_B = 56,
0086   H_TTYPE_MASK = 0xF,
0087
0088   H_EVLENGTH_MASK = 0xFFFFFF,
0089
0090   H_ERRORS_B = 24,
0091   H_ERRORS_MASK = 0xFF,
0092
0093   H_RNUMB_B = 32,
0094   H_RNUMB_MASK = 0xFFFFFF,
0095
0096   H_RTYPE_MASK = 0xFFFFFFFF,  // bits 0.. 31 of the 3rd DCC header word
0097
0098   H_DET_TTYPE_B = 32,
0099   H_DET_TTYPE_MASK = 0xFFFF,  // for bits 32.. 47 of the 3rd DCC header word
0100
0101   H_FOV_B = 48,
0102   H_FOV_MASK = 0xF,
0103
0104   H_ORBITCOUNTER_B = 0,
0105   H_ORBITCOUNTER_MASK = 0xFFFFFFFF,  // bits 0.. 31 of the 4th DCC header word
0106
0107   H_SR_B = 32,
0108   H_ZS_B = 33,
0109   H_TZS_B = 34,
0110   H_MEM_B = 35,
0111
0112   H_SRCHSTATUS_B = 36,
0113   H_CHSTATUS_MASK = 0xF,
0114
0115   H_TCC1CHSTATUS_B = 40,
0116   H_TCC2CHSTATUS_B = 44,
0117   H_TCC3CHSTATUS_B = 48,
0118   H_TCC4CHSTATUS_B = 52
0119
0120 };
0121
0122 /* 1st TTC Command */
0123 /*                 Half :       1 bits: 7                 1st Half (0), 2nd Half (1) */
0124 /*                 TE           1 bit : 6                 Test Enable Identifier */
0125 /*                 Type         2 bits: 5-4               Laser (00), LED (01) Test pulse (10), Pedestal (11) */
0126 /*                 Color        2 bits: 3-2               Blue (00), Red(01), Infrared (10), Green (11) */
0127
0128 /* 2nd TCC Command */
0129 /*                 DCC #:     6 bits: 5-0.              DCC 1 to 54. Zero means all DCC */
0130
0131 enum detailedTriggerTypeFields {
0132
0133   H_DCCID_B = 0,
0134   H_DCCID_MASK = 0x3F,
0135
0136   H_WAVEL_B = 6,
0137   H_WAVEL_MASK = 0x3,
0138
0139   H_TR_TYPE_B = 8,
0140   H_TR_TYPE_MASK = 0x7,
0141
0142   H_HALF_B = 11,
0143   H_HALF_MASK = 0x1
0144
0145 };
0146
0147 enum towerFields {
0148
0149   TOWER_ID_MASK = 0x7F,
0150
0151   TOWER_NSAMP_MASK = 0x7F,
0152   TOWER_NSAMP_B = 8,
0153
0154   TOWER_BX_MASK = 0xFFF,
0155   TOWER_BX_B = 16,
0156
0157   TOWER_L1_MASK = 0xFFF,
0158   TOWER_L1_B = 32,
0159
0160   TOWER_ADC_MASK = 0xFFF,
0161   TOWER_DIGI_MASK = 0x3FFF,
0162
0163   TOWER_STRIPID_MASK = 0x7,
0164
0165   TOWER_XTALID_MASK = 0x7,
0166   TOWER_XTALID_B = 4,
0167
0168   TOWER_LENGTH_MASK = 0x1FF,
0169   TOWER_LENGTH_B = 48
0170
0171 };
0172
0173 enum tccFields {
0174
0175   TCC_ID_MASK = 0xFF,
0176
0177   TCC_PS_B = 11,
0178
0179   TCC_BX_MASK = 0xFFF,
0180   TCC_BX_B = 16,
0181
0182   TCC_L1_MASK = 0xFFF,
0183   TCC_L1_B = 32,
0184
0185   TCC_TT_MASK = 0x7F,
0186   TCC_TT_B = 48,
0187
0188   TCC_TS_MASK = 0xF,
0189   TCC_TS_B = 55
0190
0191 };
0192
0193 enum srpFields {
0194
0195   SRP_NREAD = 0,
0196   SRP_FULLREADOUT = 3,
0197
0198   SRP_ID_MASK = 0xFF,
0199
0200   SRP_BX_MASK = 0xFFF,
0201   SRP_BX_B = 16,
0202
0203   SRP_L1_MASK = 0xFFF,
0204   SRP_L1_B = 32,
0205
0206   SRP_NFLAGS_MASK = 0x7F,
0207   SRP_NFLAGS_B = 48,
0208
0209   SRP_SRFLAG_MASK = 0x7,
0210   SRP_SRVAL_MASK = 0x3
0211
0212 };
0213
0214 enum dccFOVs {
0215   // MC raw data based on CMS NOTE 2005/021
0216   // (and raw data when FOV was unassigned, earlier than mid 2008)
0217   dcc_FOV_0 = 0,
0218
0219   // real data since ever FOV was initialized; only 2 used >= June 09
0220   dcc_FOV_1 = 1,
0221   dcc_FOV_2 = 2
0222
0223 };
0224
0225 #endif