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File indexing completed on 2021-02-14 13:15:02

0001 #ifndef EventFilter_HcalRawToDigi_interface_DeclsForKernels_h
0002 #define EventFilter_HcalRawToDigi_interface_DeclsForKernels_h
0003 
0004 #include <vector>
0005 
0006 #include "CUDADataFormats/HcalDigi/interface/DigiCollection.h"
0007 #include "HeterogeneousCore/CUDAUtilities/interface/HostAllocator.h"
0008 #include "HeterogeneousCore/CUDAUtilities/interface/device_unique_ptr.h"
0009 #include "HeterogeneousCore/CUDAUtilities/interface/host_unique_ptr.h"
0010 
0011 #include "ElectronicsMappingGPU.h"
0012 
0013 namespace hcal {
0014   namespace raw {
0015 
0016     constexpr int32_t empty_event_size = 32;
0017     constexpr uint32_t utca_nfeds_max = 50;
0018     constexpr uint32_t nbytes_per_fed_max = 10 * 1024;
0019 
0020     // each collection corresponds to a particular flavor with a certain number of
0021     // samples per digi
0022     constexpr uint32_t numOutputCollections = 3;
0023     constexpr uint8_t OutputF01HE = 0;
0024     constexpr uint8_t OutputF5HB = 1;
0025     constexpr uint8_t OutputF3HB = 2;
0026 
0027     struct ConfigurationParameters {
0028       uint32_t maxChannelsF01HE;
0029       uint32_t maxChannelsF5HB;
0030       uint32_t maxChannelsF3HB;
0031       uint32_t nsamplesF01HE;
0032       uint32_t nsamplesF5HB;
0033       uint32_t nsamplesF3HB;
0034     };
0035 
0036     struct InputDataCPU {
0037       cms::cuda::host::unique_ptr<unsigned char[]> data;
0038       cms::cuda::host::unique_ptr<uint32_t[]> offsets;
0039       cms::cuda::host::unique_ptr<int[]> feds;
0040     };
0041 
0042     struct OutputDataCPU {
0043       cms::cuda::host::unique_ptr<uint32_t[]> nchannels;
0044     };
0045 
0046     struct ScratchDataGPU {
0047       // depends on the number of output collections
0048       // that is a statically known predefined number
0049       cms::cuda::device::unique_ptr<uint32_t[]> pChannelsCounters;
0050     };
0051 
0052     struct OutputDataGPU {
0053       DigiCollection<Flavor1, ::calo::common::DevStoragePolicy> digisF01HE;
0054       DigiCollection<Flavor5, ::calo::common::DevStoragePolicy> digisF5HB;
0055       DigiCollection<Flavor3, ::calo::common::DevStoragePolicy> digisF3HB;
0056 
0057       void allocate(ConfigurationParameters const &config, cudaStream_t cudaStream) {
0058         digisF01HE.data = cms::cuda::make_device_unique<uint16_t[]>(
0059             config.maxChannelsF01HE * compute_stride<Flavor1>(config.nsamplesF01HE), cudaStream);
0060         digisF01HE.ids = cms::cuda::make_device_unique<uint32_t[]>(config.maxChannelsF01HE, cudaStream);
0061 
0062         digisF5HB.data = cms::cuda::make_device_unique<uint16_t[]>(
0063             config.maxChannelsF5HB * compute_stride<Flavor5>(config.nsamplesF5HB), cudaStream);
0064         digisF5HB.ids = cms::cuda::make_device_unique<uint32_t[]>(config.maxChannelsF5HB, cudaStream);
0065         digisF5HB.npresamples = cms::cuda::make_device_unique<uint8_t[]>(config.maxChannelsF5HB, cudaStream);
0066 
0067         digisF3HB.data = cms::cuda::make_device_unique<uint16_t[]>(
0068             config.maxChannelsF3HB * compute_stride<Flavor3>(config.nsamplesF3HB), cudaStream);
0069         digisF3HB.ids = cms::cuda::make_device_unique<uint32_t[]>(config.maxChannelsF3HB, cudaStream);
0070       }
0071     };
0072 
0073     struct InputDataGPU {
0074       cms::cuda::device::unique_ptr<unsigned char[]> data;
0075       cms::cuda::device::unique_ptr<uint32_t[]> offsets;
0076       cms::cuda::device::unique_ptr<int[]> feds;
0077     };
0078 
0079     struct ConditionsProducts {
0080       ElectronicsMappingGPU::Product const &eMappingProduct;
0081     };
0082 
0083   }  // namespace raw
0084 }  // namespace hcal
0085 
0086 #endif  // EventFilter_HcalRawToDigi_interface_DeclsForKernels_h