File indexing completed on 2024-07-31 22:58:26
0001 #ifndef FWCore_Utilities_HRRealTime_H
0002 #define FWCore_Utilities_HRRealTime_H
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0015 namespace edm {
0016 namespace details {
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0021 #if defined(__i386__)
0022
0023 static __inline__ unsigned long long rdtsc(void) {
0024 unsigned long long int x;
0025 __asm__ volatile(".byte 0x0f, 0x31" : "=A"(x));
0026 return x;
0027 }
0028 #elif defined(__x86_64__)
0029
0030 static __inline__ unsigned long long rdtsc(void) {
0031 unsigned hi, lo;
0032 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
0033 return ((unsigned long long)lo) | (((unsigned long long)hi) << 32);
0034 }
0035
0036 #elif defined(__powerpc__)
0037
0038 static __inline__ unsigned long long rdtsc(void) {
0039 unsigned long long int result = 0;
0040 unsigned long int upper, lower, tmp;
0041 __asm__ volatile(
0042 "0: \n"
0043 "\tmftbu %0 \n"
0044 "\tmftb %1 \n"
0045 "\tmftbu %2 \n"
0046 "\tcmpw %2,%0 \n"
0047 "\tbne 0b \n"
0048 : "=r"(upper), "=r"(lower), "=r"(tmp));
0049 result = upper;
0050 result = result << 32;
0051 result = result | lower;
0052
0053 return (result);
0054 }
0055 #elif defined(__arm__)
0056 #warning unsigned long long rdtsc(void) is not implemented on ARMv7 architecture. Returning 0 by default.
0057 static __inline__ unsigned long long rdtsc(void) { return 0; }
0058 #elif defined(__aarch64__)
0059 static __inline__ unsigned long long rdtsc(void) {
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0075 unsigned long long ret;
0076 __asm__ __volatile__("isb; mrs %0, cntvct_el0" : "=r"(ret));
0077 return ret;
0078 }
0079 #elif defined(__riscv) && __riscv_xlen == 64
0080 static __inline__ unsigned long long rdtsc(void) {
0081 unsigned long long cycles;
0082 asm volatile("rdcycle %0" : "=r"(cycles));
0083 return cycles;
0084 }
0085 #else
0086 #error The file FWCore/Utilities/interface/HRRealTime.h needs to be set up for your CPU type.
0087 #endif
0088 }
0089 }
0090
0091 namespace edm {
0092
0093 typedef long long int HRTimeDiffType;
0094 typedef unsigned long long int HRTimeType;
0095
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0097 inline HRTimeType hrRealTime() { return details::rdtsc(); }
0098
0099 }
0100
0101 #endif