Back to home page

Project CMSSW displayed by LXR

 
 

    


File indexing completed on 2022-04-20 23:56:49

0001 import FWCore.ParameterSet.Config as cms
0002 
0003 hltDt1DRecHits = cms.EDProducer("DTRecHitProducer",
0004     debug = cms.untracked.bool(False),
0005     dtDigiLabel = cms.InputTag("simMuonDTDigis"),
0006     recAlgo = cms.string('DTLinearDriftFromDBAlgo'),
0007     recAlgoConfig = cms.PSet(
0008         debug = cms.untracked.bool(False),
0009         doVdriftCorr = cms.bool(True),
0010         maxTime = cms.double(420.0),
0011         minTime = cms.double(-3.0),
0012         readLegacyTTrigDB = cms.bool(True),
0013         readLegacyVDriftDB = cms.bool(True),
0014         stepTwoFromDigi = cms.bool(False),
0015         tTrigMode = cms.string('DTTTrigSyncFromDB'),
0016         tTrigModeConfig = cms.PSet(
0017             debug = cms.untracked.bool(False),
0018             doT0Correction = cms.bool(True),
0019             doTOFCorrection = cms.bool(True),
0020             doWirePropCorrection = cms.bool(True),
0021             tTrigLabel = cms.string(''),
0022             t0Label = cms.string(''),
0023             tofCorrType = cms.int32(0),
0024             vPropWire = cms.double(24.4),
0025             wirePropCorrType = cms.int32(0)
0026         ),
0027         useUncertDB = cms.bool(True)
0028     )
0029 )