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0001 // -*- C++ -*-
0002 //
0003 // Package:     L1Trigger/CSCTrackFinder
0004 // Class  :     parameters
0005 //
0006 // Implementation:
0007 //     [Notes on implementation]
0008 //
0009 // Original Author:  Christopher Jones
0010 //         Created:  Thu, 27 May 2021 20:02:26 GMT
0011 //
0012 
0013 // system include files
0014 
0015 // user include files
0016 #include "parameters.h"
0017 #include "CondFormats/L1TObjects/interface/L1MuCSCTFConfiguration.h"
0018 #include "FWCore/ParameterSet/interface/ParameterSet.h"
0019 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0020 
0021 #include <sstream>
0022 
0023 edm::ParameterSet parameters(L1MuCSCTFConfiguration const& iConfig, int sp) {
0024   LogDebug("L1MuCSCTFConfiguration") << "SP:" << int(sp) << std::endl;
0025 
0026   edm::ParameterSet pset;
0027   if (sp >= 12)
0028     return pset;
0029 
0030   // ------------------------------------------------------
0031   // core configuration
0032   // by default everything is disabled: we need to set them
0033   // coincidence and singles
0034   bool run_core = false;
0035   bool trigger_on_ME1a = false;
0036   bool trigger_on_ME1b = false;
0037   bool trigger_on_ME2 = false;
0038   bool trigger_on_ME3 = false;
0039   bool trigger_on_ME4 = false;
0040   bool trigger_on_MB1a = false;
0041   bool trigger_on_MB1d = false;
0042 
0043   unsigned int BXAdepth = 0;
0044   unsigned int useDT = 0;
0045   unsigned int widePhi = 0;
0046   unsigned int PreTrigger = 0;
0047   // ------------------------------------------------------
0048 
0049   // ------------------------------------------------------
0050   // these are very important parameters.
0051   // Double check with Alex
0052   unsigned int CoreLatency = 7;
0053   bool rescaleSinglesPhi = true;
0054 
0055   // ask Alex if use or remove them or what
0056   bool AllowALCTonly = false;
0057   bool AllowCLCTonly = false;
0058 
0059   // other useful parameters in general not set in the OMDS
0060   unsigned int QualityEnableME1a = 0xFFFF;
0061   unsigned int QualityEnableME1b = 0xFFFF;
0062   unsigned int QualityEnableME1c = 0xFFFF;
0063   unsigned int QualityEnableME1d = 0xFFFF;
0064   unsigned int QualityEnableME1e = 0xFFFF;
0065   unsigned int QualityEnableME1f = 0xFFFF;
0066   unsigned int QualityEnableME2a = 0xFFFF;
0067   unsigned int QualityEnableME2b = 0xFFFF;
0068   unsigned int QualityEnableME2c = 0xFFFF;
0069   unsigned int QualityEnableME3a = 0xFFFF;
0070   unsigned int QualityEnableME3b = 0xFFFF;
0071   unsigned int QualityEnableME3c = 0xFFFF;
0072   unsigned int QualityEnableME4a = 0xFFFF;
0073   unsigned int QualityEnableME4b = 0xFFFF;
0074   unsigned int QualityEnableME4c = 0xFFFF;
0075 
0076   unsigned int kill_fiber = 0;
0077   unsigned int singlesTrackOutput = 1;
0078   // ------------------------------------------------------
0079 
0080   //initialization of the DAT_ETA registers with default values
0081   //the DAT_ETA registers meaning are explained at Table 2 of
0082   //http://www.phys.ufl.edu/~uvarov/SP05/LU-SP_ReferenceGuide_090915_Update.pdf
0083   std::vector<unsigned int> etamin(8), etamax(8), etawin(7);
0084 
0085   unsigned int mindetap = 8;
0086   unsigned int mindetap_halo = 8;
0087 
0088   etamin[0] = 22;
0089   etamin[1] = 22;
0090   etamin[2] = 14;
0091   etamin[3] = 14;
0092   etamin[4] = 14;
0093   etamin[5] = 14;
0094   etamin[6] = 10;
0095   etamin[7] = 22;
0096 
0097   unsigned int mindeta12_accp = 8;
0098   unsigned int mindeta13_accp = 19;
0099   unsigned int mindeta112_accp = 19;
0100   unsigned int mindeta113_accp = 30;
0101 
0102   etamax[0] = 127;
0103   etamax[1] = 127;
0104   etamax[2] = 127;
0105   etamax[3] = 127;
0106   etamax[4] = 127;
0107   etamax[5] = 24;
0108   etamax[6] = 24;
0109   etamax[7] = 127;
0110 
0111   unsigned int maxdeta12_accp = 14;
0112   unsigned int maxdeta13_accp = 25;
0113   unsigned int maxdeta112_accp = 25;
0114   unsigned int maxdeta113_accp = 36;
0115 
0116   etawin[0] = 4;
0117   etawin[1] = 4;
0118   etawin[2] = 4;
0119   etawin[3] = 4;
0120   etawin[4] = 4;
0121   etawin[5] = 4;
0122   etawin[6] = 4;
0123 
0124   unsigned int maxdphi12_accp = 64;
0125   unsigned int maxdphi13_accp = 64;
0126   unsigned int maxdphi112_accp = 64;
0127   unsigned int maxdphi113_accp = 64;
0128 
0129   unsigned int mindphip = 128;
0130   unsigned int mindphip_halo = 128;
0131 
0132   unsigned int straightp = 60;
0133   unsigned int curvedp = 200;
0134 
0135   unsigned int mbaPhiOff = 0;
0136   // this differ from the default value in the documentation because during
0137   // craft 09 it mbbPhiOff, as well as mbaPhiOff were not existing, thus set to 0 (they are offsets)
0138   // and for backward compatibility it needs to be set to 0. Anyway mbbPhiOff since its introduction in the
0139   // core will have to be ALWAYS part of the configuration, so it won't be never initialized to the
0140   // default value 2048.
0141   unsigned int mbbPhiOff = 0;
0142 
0143   int eta_cnt = 0;
0144 
0145   // default firmware versions (the ones used from run 132440)
0146   unsigned int firmwareSP = 20100210;
0147   unsigned int firmwareFA = 20090521;
0148   unsigned int firmwareDD = 20090521;
0149   unsigned int firmwareVM = 20090521;
0150 
0151   // default printout
0152   LogDebug("L1MuCSCTFConfiguration")
0153       << "\nCORE CONFIGURATION  DEFAULT VALUES"
0154       << "\nrun_core=" << run_core << "\ntrigger_on_ME1a=" << trigger_on_ME1a << "\ntrigger_on_ME1b=" << trigger_on_ME1b
0155       << "\ntrigger_on_ME2=" << trigger_on_ME2 << "\ntrigger_on_ME3=" << trigger_on_ME3
0156       << "\ntrigger_on_ME4=" << trigger_on_ME4 << "\ntrigger_on_MB1a=" << trigger_on_MB1a
0157       << "\ntrigger_on_MB1d=" << trigger_on_MB1d
0158 
0159       << "\nBXAdepth=" << BXAdepth << "\nuseDT=" << useDT << "\nwidePhi=" << widePhi << "\nPreTrigger=" << PreTrigger
0160 
0161       << "\nCoreLatency=" << CoreLatency << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
0162 
0163       << "\n\nVARIOUS CONFIGURATION PARAMETERS DEFAULT VALUES"
0164       << "\nAllowALCTonly=" << AllowALCTonly << "\nAllowCLCTonly=" << AllowCLCTonly
0165 
0166       << "\nQualityEnableME1a=" << QualityEnableME1a << "\nQualityEnableME1b=" << QualityEnableME1b
0167       << "\nQualityEnableME1c=" << QualityEnableME1c << "\nQualityEnableME1d=" << QualityEnableME1d
0168       << "\nQualityEnableME1e=" << QualityEnableME1e << "\nQualityEnableME1f=" << QualityEnableME1f
0169       << "\nQualityEnableME2a=" << QualityEnableME2a << "\nQualityEnableME2b=" << QualityEnableME2b
0170       << "\nQualityEnableME2c=" << QualityEnableME2c << "\nQualityEnableME3a=" << QualityEnableME3a
0171       << "\nQualityEnableME3b=" << QualityEnableME3b << "\nQualityEnableME3c=" << QualityEnableME3c
0172       << "\nQualityEnableME4a=" << QualityEnableME4a << "\nQualityEnableME4b=" << QualityEnableME4b
0173       << "\nQualityEnableME4c=" << QualityEnableME4c
0174 
0175       << "\nkill_fiber=" << kill_fiber << "\nsinglesTrackOutput=" << singlesTrackOutput
0176 
0177       << "\n\nDEFAULT VALUES FOR DAT_ETA"
0178       << "\nmindetap     =" << mindetap << "\nmindetap_halo=" << mindetap_halo
0179 
0180       << "\netamin[0]=" << etamin[0] << "\netamin[1]=" << etamin[1] << "\netamin[2]=" << etamin[2]
0181       << "\netamin[3]=" << etamin[3] << "\netamin[4]=" << etamin[4] << "\netamin[5]=" << etamin[5]
0182       << "\netamin[6]=" << etamin[6] << "\netamin[7]=" << etamin[7]
0183 
0184       << "\nmindeta12_accp =" << mindeta12_accp << "\nmindeta13_accp =" << mindeta13_accp
0185       << "\nmindeta112_accp=" << mindeta112_accp << "\nmindeta113_accp=" << mindeta113_accp
0186 
0187       << "\netamax[0]=" << etamax[0] << "\netamax[1]=" << etamax[1] << "\netamax[2]=" << etamax[2]
0188       << "\netamax[3]=" << etamax[3] << "\netamax[4]=" << etamax[4] << "\netamax[5]=" << etamax[5]
0189       << "\netamax[6]=" << etamax[6] << "\netamax[7]=" << etamax[7]
0190 
0191       << "\nmaxdeta12_accp =" << maxdeta12_accp << "\nmaxdeta13_accp =" << maxdeta13_accp
0192       << "\nmaxdeta112_accp=" << maxdeta112_accp << "\nmaxdeta113_accp=" << maxdeta113_accp
0193 
0194       << "\netawin[0]=" << etawin[0] << "\netawin[1]=" << etawin[1] << "\netawin[2]=" << etawin[2]
0195       << "\netawin[3]=" << etawin[3] << "\netawin[4]=" << etawin[4] << "\netawin[5]=" << etawin[5]
0196       << "\netawin[6]=" << etawin[6]
0197 
0198       << "\nmaxdphi12_accp =" << maxdphi12_accp << "\nmaxdphi13_accp =" << maxdphi13_accp
0199       << "\nmaxdphi112_accp=" << maxdphi112_accp << "\nmaxdphi113_accp=" << maxdphi113_accp
0200 
0201       << "\nmindphip     =" << mindphip << "\nmindphip_halo=" << mindphip_halo
0202 
0203       << "\nstraightp=" << straightp << "\ncurvedp  =" << curvedp << "\nmbaPhiOff=" << mbaPhiOff
0204       << "\nmbbPhiOff=" << mbbPhiOff
0205 
0206       << "\n\nFIRMWARE VERSIONS"
0207       << "\nSP: " << firmwareSP << "\nFA: " << firmwareFA << "\nDD: " << firmwareDD << "\nVM: " << firmwareVM;
0208 
0209   // start filling the registers with the values in the DBS
0210   std::stringstream conf(iConfig[sp]);
0211   while (!conf.eof()) {
0212     char buff[1024];
0213     conf.getline(buff, 1024);
0214     std::stringstream line(buff);
0215     //std::cout<<"buff:"<<buff<<std::endl;
0216     std::string register_;
0217     line >> register_;
0218     std::string chip_;
0219     line >> chip_;
0220     std::string muon_;
0221     line >> muon_;
0222     std::string writeValue_;
0223     line >> writeValue_;
0224     std::string comments_;
0225     std::getline(line, comments_);
0226 
0227     if (register_ == "CSR_REQ" && chip_ == "SP") {
0228       unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
0229       run_core = (value & 0x8000);
0230       trigger_on_ME1a = (value & 0x0001);
0231       trigger_on_ME1b = (value & 0x0002);
0232       trigger_on_ME2 = (value & 0x0004);
0233       trigger_on_ME3 = (value & 0x0008);
0234       trigger_on_ME4 = (value & 0x0010);
0235       trigger_on_MB1a = (value & 0x0100);
0236       trigger_on_MB1d = (value & 0x0200);
0237     }
0238 
0239     if (register_ == "CSR_SCC" && chip_ == "SP") {
0240       unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
0241 
0242       BXAdepth = (value & 0x3);
0243       useDT = ((value & 0x80) >> 7);
0244       widePhi = ((value & 0x40) >> 6);
0245       PreTrigger = ((value & 0x300) >> 8);
0246     }
0247 
0248     if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M1")
0249       QualityEnableME1a = ::strtol(writeValue_.c_str(), nullptr, 16);
0250     if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M2")
0251       QualityEnableME1b = ::strtol(writeValue_.c_str(), nullptr, 16);
0252     if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M3")
0253       QualityEnableME1c = ::strtol(writeValue_.c_str(), nullptr, 16);
0254     if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M1")
0255       QualityEnableME1d = ::strtol(writeValue_.c_str(), nullptr, 16);
0256     if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M2")
0257       QualityEnableME1e = ::strtol(writeValue_.c_str(), nullptr, 16);
0258     if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M3")
0259       QualityEnableME1f = ::strtol(writeValue_.c_str(), nullptr, 16);
0260     if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M1")
0261       QualityEnableME2a = ::strtol(writeValue_.c_str(), nullptr, 16);
0262     if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M2")
0263       QualityEnableME2b = ::strtol(writeValue_.c_str(), nullptr, 16);
0264     if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M3")
0265       QualityEnableME2c = ::strtol(writeValue_.c_str(), nullptr, 16);
0266     if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M1")
0267       QualityEnableME3a = ::strtol(writeValue_.c_str(), nullptr, 16);
0268     if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M2")
0269       QualityEnableME3b = ::strtol(writeValue_.c_str(), nullptr, 16);
0270     if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M3")
0271       QualityEnableME3c = ::strtol(writeValue_.c_str(), nullptr, 16);
0272     if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M1")
0273       QualityEnableME4a = ::strtol(writeValue_.c_str(), nullptr, 16);
0274     if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M2")
0275       QualityEnableME4b = ::strtol(writeValue_.c_str(), nullptr, 16);
0276     if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M3")
0277       QualityEnableME4c = ::strtol(writeValue_.c_str(), nullptr, 16);
0278 
0279     if (register_ == "CSR_KFL")
0280       kill_fiber = ::strtol(writeValue_.c_str(), nullptr, 16);
0281 
0282     if (register_ == "CSR_SFC" && chip_ == "SP") {
0283       unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
0284       singlesTrackOutput = ((value & 0x3000) >> 12);
0285     }
0286 
0287     if (register_ == "CNT_ETA" && chip_ == "SP") {
0288       unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
0289       eta_cnt = value;
0290     }
0291 
0292     // LATEST VERSION FROM CORE 2010-01-22 at http://www.phys.ufl.edu/~madorsky/sp/2010-01-22
0293     if (register_ == "DAT_ETA" && chip_ == "SP") {
0294       unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
0295 
0296       //std::cout<<"DAT_ETA SP value:"<<value<<std::endl;
0297 
0298       if (eta_cnt == 0)
0299         mindetap = value;
0300       if (eta_cnt == 1)
0301         mindetap_halo = value;
0302 
0303       if (eta_cnt >= 2 && eta_cnt < 10)
0304         etamin[eta_cnt - 2] = value;
0305 
0306       if (eta_cnt == 10)
0307         mindeta12_accp = value;
0308       if (eta_cnt == 11)
0309         mindeta13_accp = value;
0310       if (eta_cnt == 12)
0311         mindeta112_accp = value;
0312       if (eta_cnt == 13)
0313         mindeta113_accp = value;
0314 
0315       if (eta_cnt >= 14 && eta_cnt < 22)
0316         etamax[eta_cnt - 14] = value;
0317 
0318       if (eta_cnt == 22)
0319         maxdeta12_accp = value;
0320       if (eta_cnt == 23)
0321         maxdeta13_accp = value;
0322       if (eta_cnt == 24)
0323         maxdeta112_accp = value;
0324       if (eta_cnt == 25)
0325         maxdeta113_accp = value;
0326 
0327       if (eta_cnt >= 26 && eta_cnt < 33)
0328         etawin[eta_cnt - 26] = value;
0329 
0330       if (eta_cnt == 33)
0331         maxdphi12_accp = value;
0332       if (eta_cnt == 34)
0333         maxdphi13_accp = value;
0334       if (eta_cnt == 35)
0335         maxdphi112_accp = value;
0336       if (eta_cnt == 36)
0337         maxdphi113_accp = value;
0338 
0339       if (eta_cnt == 37)
0340         mindphip = value;
0341       if (eta_cnt == 38)
0342         mindphip_halo = value;
0343 
0344       if (eta_cnt == 39)
0345         straightp = value;
0346       if (eta_cnt == 40)
0347         curvedp = value;
0348       if (eta_cnt == 41)
0349         mbaPhiOff = value;
0350       if (eta_cnt == 42)
0351         mbbPhiOff = value;
0352 
0353       eta_cnt++;
0354     }
0355 
0356     // filling the firmware variables: SP MEZZANINE
0357     if (register_ == "FIRMWARE" && muon_ == "SP") {
0358       unsigned int value = atoi(writeValue_.c_str());
0359       firmwareSP = value;
0360     }
0361 
0362     // filling the firmware variables: Front FPGAs
0363     if (register_ == "FIRMWARE" && muon_ == "FA") {
0364       unsigned int value = atoi(writeValue_.c_str());
0365       firmwareFA = value;
0366     }
0367 
0368     // filling the firmware variables: DDU
0369     if (register_ == "FIRMWARE" && muon_ == "DD") {
0370       unsigned int value = atoi(writeValue_.c_str());
0371       firmwareDD = value;
0372     }
0373 
0374     // filling the firmware variables: VM
0375     if (register_ == "FIRMWARE" && muon_ == "VM") {
0376       unsigned int value = atoi(writeValue_.c_str());
0377       firmwareVM = value;
0378     }
0379   }
0380 
0381   pset.addParameter<bool>("run_core", run_core);
0382   pset.addParameter<bool>("trigger_on_ME1a", trigger_on_ME1a);
0383   pset.addParameter<bool>("trigger_on_ME1b", trigger_on_ME1b);
0384   pset.addParameter<bool>("trigger_on_ME2", trigger_on_ME2);
0385   pset.addParameter<bool>("trigger_on_ME3", trigger_on_ME3);
0386   pset.addParameter<bool>("trigger_on_ME4", trigger_on_ME4);
0387   pset.addParameter<bool>("trigger_on_MB1a", trigger_on_MB1a);
0388   pset.addParameter<bool>("trigger_on_MB1d", trigger_on_MB1d);
0389 
0390   pset.addParameter<unsigned int>("BXAdepth", BXAdepth);
0391   pset.addParameter<unsigned int>("useDT", useDT);
0392   pset.addParameter<unsigned int>("widePhi", widePhi);
0393   pset.addParameter<unsigned int>("PreTrigger", PreTrigger);
0394 
0395   // this were two old settings, not used anymore. Set them to zero
0396   // ask Alex if he can remove them altogether
0397   pset.addParameter<bool>("AllowALCTonly", AllowALCTonly);
0398   pset.addParameter<bool>("AllowCLCTonly", AllowCLCTonly);
0399 
0400   pset.addParameter<int>("CoreLatency", CoreLatency);
0401   pset.addParameter<bool>("rescaleSinglesPhi", rescaleSinglesPhi);
0402 
0403   pset.addParameter<unsigned int>("QualityEnableME1a", QualityEnableME1a);
0404   pset.addParameter<unsigned int>("QualityEnableME1b", QualityEnableME1b);
0405   pset.addParameter<unsigned int>("QualityEnableME1c", QualityEnableME1c);
0406   pset.addParameter<unsigned int>("QualityEnableME1d", QualityEnableME1d);
0407   pset.addParameter<unsigned int>("QualityEnableME1e", QualityEnableME1e);
0408   pset.addParameter<unsigned int>("QualityEnableME1f", QualityEnableME1f);
0409   pset.addParameter<unsigned int>("QualityEnableME2a", QualityEnableME2a);
0410   pset.addParameter<unsigned int>("QualityEnableME2b", QualityEnableME2b);
0411   pset.addParameter<unsigned int>("QualityEnableME2c", QualityEnableME2c);
0412   pset.addParameter<unsigned int>("QualityEnableME3a", QualityEnableME3a);
0413   pset.addParameter<unsigned int>("QualityEnableME3b", QualityEnableME3b);
0414   pset.addParameter<unsigned int>("QualityEnableME3c", QualityEnableME3c);
0415   pset.addParameter<unsigned int>("QualityEnableME4a", QualityEnableME4a);
0416   pset.addParameter<unsigned int>("QualityEnableME4b", QualityEnableME4b);
0417   pset.addParameter<unsigned int>("QualityEnableME4c", QualityEnableME4c);
0418 
0419   pset.addParameter<unsigned int>("kill_fiber", kill_fiber);
0420   pset.addParameter<unsigned int>("singlesTrackOutput", singlesTrackOutput);
0421 
0422   // add the DAT_ETA registers to the pset
0423   pset.addParameter<unsigned int>("mindetap", mindetap);
0424   pset.addParameter<unsigned int>("mindetap_halo", mindetap_halo);
0425 
0426   pset.addParameter<std::vector<unsigned int> >("EtaMin", etamin);
0427 
0428   pset.addParameter<unsigned int>("mindeta12_accp", mindeta12_accp);
0429   pset.addParameter<unsigned int>("mindeta13_accp", mindeta13_accp);
0430   pset.addParameter<unsigned int>("mindeta112_accp", mindeta112_accp);
0431   pset.addParameter<unsigned int>("mindeta113_accp", mindeta113_accp);
0432 
0433   pset.addParameter<std::vector<unsigned int> >("EtaMax", etamax);
0434 
0435   pset.addParameter<unsigned int>("maxdeta12_accp", maxdeta12_accp);
0436   pset.addParameter<unsigned int>("maxdeta13_accp", maxdeta13_accp);
0437   pset.addParameter<unsigned int>("maxdeta112_accp", maxdeta112_accp);
0438   pset.addParameter<unsigned int>("maxdeta113_accp", maxdeta113_accp);
0439 
0440   pset.addParameter<std::vector<unsigned int> >("EtaWindows", etawin);
0441 
0442   pset.addParameter<unsigned int>("maxdphi12_accp", maxdphi12_accp);
0443   pset.addParameter<unsigned int>("maxdphi13_accp", maxdphi13_accp);
0444   pset.addParameter<unsigned int>("maxdphi112_accp", maxdphi112_accp);
0445   pset.addParameter<unsigned int>("maxdphi113_accp", maxdphi113_accp);
0446 
0447   pset.addParameter<unsigned int>("mindphip", mindphip);
0448   pset.addParameter<unsigned int>("mindphip_halo", mindphip_halo);
0449 
0450   pset.addParameter<unsigned int>("straightp", straightp);
0451   pset.addParameter<unsigned int>("curvedp", curvedp);
0452   pset.addParameter<unsigned int>("mbaPhiOff", mbaPhiOff);
0453   pset.addParameter<unsigned int>("mbbPhiOff", mbbPhiOff);
0454 
0455   pset.addParameter<unsigned int>("firmwareSP", firmwareSP);
0456   pset.addParameter<unsigned int>("firmwareFA", firmwareFA);
0457   pset.addParameter<unsigned int>("firmwareDD", firmwareDD);
0458   pset.addParameter<unsigned int>("firmwareVM", firmwareVM);
0459 
0460   // printout
0461   LogDebug("L1MuCSCTFConfiguration")
0462       << "\nCORE CONFIGURATION AFTER READING THE DBS VALUES"
0463       << "\nrun_core=" << run_core << "\ntrigger_on_ME1a=" << trigger_on_ME1a << "\ntrigger_on_ME1b=" << trigger_on_ME1b
0464       << "\ntrigger_on_ME2=" << trigger_on_ME2 << "\ntrigger_on_ME3=" << trigger_on_ME3
0465       << "\ntrigger_on_ME4=" << trigger_on_ME4 << "\ntrigger_on_MB1a=" << trigger_on_MB1a
0466       << "\ntrigger_on_MB1d=" << trigger_on_MB1d
0467 
0468       << "\nBXAdepth=" << BXAdepth << "\nuseDT=" << useDT << "\nwidePhi=" << widePhi << "\nPreTrigger=" << PreTrigger
0469 
0470       << "\nCoreLatency=" << CoreLatency << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
0471 
0472       << "\n\nVARIOUS CONFIGURATION PARAMETERS AFTER READING THE DBS VALUES"
0473       << "\nAllowALCTonly=" << AllowALCTonly << "\nAllowCLCTonly=" << AllowCLCTonly
0474 
0475       << "\nQualityEnableME1a=" << QualityEnableME1a << "\nQualityEnableME1b=" << QualityEnableME1b
0476       << "\nQualityEnableME1c=" << QualityEnableME1c << "\nQualityEnableME1d=" << QualityEnableME1d
0477       << "\nQualityEnableME1e=" << QualityEnableME1e << "\nQualityEnableME1f=" << QualityEnableME1f
0478       << "\nQualityEnableME2a=" << QualityEnableME2a << "\nQualityEnableME2b=" << QualityEnableME2b
0479       << "\nQualityEnableME2c=" << QualityEnableME2c << "\nQualityEnableME3a=" << QualityEnableME3a
0480       << "\nQualityEnableME3b=" << QualityEnableME3b << "\nQualityEnableME3c=" << QualityEnableME3c
0481       << "\nQualityEnableME4a=" << QualityEnableME4a << "\nQualityEnableME4b=" << QualityEnableME4b
0482       << "\nQualityEnableME4c=" << QualityEnableME4c
0483 
0484       << "\nkill_fiber=" << kill_fiber << "\nsinglesTrackOutput=" << singlesTrackOutput
0485 
0486       << "\n\nDAT_ETA AFTER READING THE DBS VALUES"
0487       << "\nmindetap     =" << mindetap << "\nmindetap_halo=" << mindetap_halo
0488 
0489       << "\netamin[0]=" << etamin[0] << "\netamin[1]=" << etamin[1] << "\netamin[2]=" << etamin[2]
0490       << "\netamin[3]=" << etamin[3] << "\netamin[4]=" << etamin[4] << "\netamin[5]=" << etamin[5]
0491       << "\netamin[6]=" << etamin[6] << "\netamin[7]=" << etamin[7]
0492 
0493       << "\nmindeta12_accp =" << mindeta12_accp << "\nmindeta13_accp =" << mindeta13_accp
0494       << "\nmindeta112_accp=" << mindeta112_accp << "\nmindeta113_accp=" << mindeta113_accp
0495 
0496       << "\netamax[0]=" << etamax[0] << "\netamax[1]=" << etamax[1] << "\netamax[2]=" << etamax[2]
0497       << "\netamax[3]=" << etamax[3] << "\netamax[4]=" << etamax[4] << "\netamax[5]=" << etamax[5]
0498       << "\netamax[6]=" << etamax[6] << "\netamax[7]=" << etamax[7]
0499 
0500       << "\nmaxdeta12_accp =" << maxdeta12_accp << "\nmaxdeta13_accp =" << maxdeta13_accp
0501       << "\nmaxdeta112_accp=" << maxdeta112_accp << "\nmaxdeta113_accp=" << maxdeta113_accp
0502 
0503       << "\netawin[0]=" << etawin[0] << "\netawin[1]=" << etawin[1] << "\netawin[2]=" << etawin[2]
0504       << "\netawin[3]=" << etawin[3] << "\netawin[4]=" << etawin[4] << "\netawin[5]=" << etawin[5]
0505       << "\netawin[6]=" << etawin[6]
0506 
0507       << "\nmaxdphi12_accp =" << maxdphi12_accp << "\nmaxdphi13_accp =" << maxdphi13_accp
0508       << "\nmaxdphi112_accp=" << maxdphi112_accp << "\nmaxdphi113_accp=" << maxdphi113_accp
0509 
0510       << "\nmindphip     =" << mindphip << "\nmindphip_halo=" << mindphip_halo
0511 
0512       << "\nstraightp=" << straightp << "\ncurvedp  =" << curvedp << "\nmbaPhiOff=" << mbaPhiOff
0513       << "\nmbbPhiOff=" << mbbPhiOff
0514 
0515       << "\n\nFIRMWARE VERSIONS AFTER READING THE DBS VALUES"
0516       << "\nSP: " << firmwareSP << "\nFA: " << firmwareFA << "\nDD: " << firmwareDD << "\nVM: " << firmwareVM;
0517 
0518   // ---------------------------------------------------------
0519 
0520   return pset;
0521 }
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