File indexing completed on 2024-04-06 12:21:55
0001 #ifndef L1Trigger_TrackFindingTracklet_interface_Projection_h
0002 #define L1Trigger_TrackFindingTracklet_interface_Projection_h
0003
0004 #include "L1Trigger/TrackFindingTracklet/interface/FPGAWord.h"
0005
0006 namespace trklet {
0007
0008 class Settings;
0009
0010 class Projection {
0011 public:
0012 Projection() { valid_ = false; }
0013
0014 ~Projection() = default;
0015
0016 void init(Settings const& settings,
0017 unsigned int layerdisk,
0018 int iphiproj,
0019 int irzproj,
0020 int iphider,
0021 int irzder,
0022 double phiproj,
0023 double rzproj,
0024 double phiprojder,
0025 double rzprojder,
0026 double phiprojapprox,
0027 double rzprojapprox,
0028 double phiprojderapprox,
0029 double rzprojderapprox,
0030 bool isPSseed);
0031
0032 bool valid() const { return valid_; }
0033
0034 unsigned int layerdisk() const {
0035 assert(valid_);
0036 return layerdisk_;
0037 };
0038
0039 const FPGAWord& fpgaphiproj() const {
0040 assert(valid_);
0041 return fpgaphiproj_;
0042 };
0043
0044 const FPGAWord& fpgarzproj() const {
0045 assert(valid_);
0046 return fpgarzproj_;
0047 };
0048
0049 const FPGAWord& fpgaphiprojder() const {
0050 assert(valid_);
0051 return fpgaphiprojder_;
0052 };
0053
0054 const FPGAWord& fpgarzprojder() const {
0055 assert(valid_);
0056 return fpgarzprojder_;
0057 };
0058
0059 const FPGAWord& fpgarzbin1projvm() const {
0060 assert(valid_);
0061 return fpgarzbin1projvm_;
0062 };
0063
0064 const FPGAWord& fpgarzbin2projvm() const {
0065 assert(valid_);
0066 return fpgarzbin2projvm_;
0067 };
0068
0069 const FPGAWord& fpgafinerzvm() const {
0070 assert(valid_);
0071 return fpgafinerzvm_;
0072 };
0073
0074 const FPGAWord& fpgafinephivm() const {
0075 assert(valid_);
0076 return fpgafinephivm_;
0077 };
0078
0079 double phiproj() const {
0080 assert(valid_);
0081 return phiproj_;
0082 };
0083
0084 double rzproj() const {
0085 assert(valid_);
0086 return rzproj_;
0087 };
0088
0089 double phiprojder() const {
0090 assert(valid_);
0091 return phiprojder_;
0092 };
0093
0094 double rzprojder() const {
0095 assert(valid_);
0096 return rzprojder_;
0097 };
0098
0099 double phiprojapprox() const {
0100 assert(valid_);
0101 return phiprojapprox_;
0102 };
0103
0104 double rzprojapprox() const {
0105 assert(valid_);
0106 return rzprojapprox_;
0107 };
0108
0109 double phiprojderapprox() const {
0110 assert(valid_);
0111 return phiprojderapprox_;
0112 };
0113
0114 double rzprojderapprox() const {
0115 assert(valid_);
0116 return rzprojderapprox_;
0117 };
0118
0119 void setBendIndex(int bendindex) { fpgabendindex_.set(bendindex, 5, true, __LINE__, __FILE__); }
0120
0121 const FPGAWord& getBendIndex() const { return fpgabendindex_; }
0122
0123 protected:
0124 bool valid_;
0125
0126 unsigned int layerdisk_;
0127
0128 FPGAWord fpgaphiproj_;
0129 FPGAWord fpgarzproj_;
0130 FPGAWord fpgaphiprojder_;
0131 FPGAWord fpgarzprojder_;
0132
0133 FPGAWord fpgarzbin1projvm_;
0134 FPGAWord fpgarzbin2projvm_;
0135 FPGAWord fpgafinerzvm_;
0136 FPGAWord fpgafinephivm_;
0137
0138 double phiproj_;
0139 double rzproj_;
0140 double phiprojder_;
0141 double rzprojder_;
0142
0143 double phiprojapprox_;
0144 double rzprojapprox_;
0145 double phiprojderapprox_;
0146 double rzprojderapprox_;
0147
0148
0149 FPGAWord fpgabendindex_;
0150 };
0151 };
0152 #endif