Warning, /L1TriggerConfig/L1GtConfigProducers/data/VhdlTemplates/InternalTemplates/header is written in an unsupported language. File is not indexed.
0001 -- **************************
0002 -- INSTITUTION: Hephy Vienna
0003 -- LOGIC CORE: GTL-module condition chip logic
0004 -- VHDL-LIBRARY: $(vhdl_path)
0005 -- MODULE NAME: $(vhdl_file_name)
0006 -- GTL SETUP NAME: $(gtl_setup_name)
0007 -- VERSION: $(version)
0008 -- DESIGNER: $(designer_name)
0009 -- DATE: $(designer_date)
0010 -- REMARKS: $(designer_comments)
0011 -- CALO INPUTS FOR CONDITION CHIP 1:
0012 $(connected_channels_1)
0013 -- CALO INPUTS FOR CONDITION CHIP 1:
0014 $(connected_channels_2)
0015 -- **************************
