Warning, /L1TriggerConfig/L1GtConfigProducers/data/VhdlTemplates/Templates/cond_chip.vhd is written in an unsupported language. File is not indexed.
0001 $(header)
0002
0003 ------------------------------------------------------------
0004 -- --
0005 -- LOGIC CORE: GTL-9U-module condition/algo chip logic --
0006 -- MODULE NAME: cond_chip --
0007 -- INSTITUTION: Hephy Vienna --
0008 -- DESIGNER: H. Bergauer --
0009 -- --
0010 -- VHDL-LIBRARY VERSION: V11.x --
0011 -- DATE: 02 2008 --
0012 -- --
0013 -- FUNCTIONAL DESCRIPTION: --
0014 -- top of hierarchy for condition-chip logic of GTL-9U --
0015 -- --
0016 -- REVISION HISTORY: --
0017 -- Version: HB160306 --
0018 -- |--> algo-memory as dual port memory with --
0019 -- | 6 x 1024 x 16 bits (16 bits vdata) --
0020 -- |--> PLL for 80 MHz clock for calo/muon input data --
0021 -- |--> DTACK for calos and muons --
0022 -- |--> no BERR generated --
0023 -- Version: HB301107 --
0024 -- |--> rw-register with parameters for read, dtack, --
0025 -- and default-values (with reset-option) --
0026 -- Version: HB150208 --
0027 -- |--> INCLOCK_PERIOD implemented --
0028 -- --
0029 ------------------------------------------------------------
0030 LIBRARY ieee;
0031 USE ieee.std_logic_1164.ALL;
0032 LIBRARY altera;
0033 USE altera.maxplus2.ALL;
0034
0035 -- for "altclklock" - HB111105
0036 LIBRARY altera_mf;
0037 USE altera_mf.altera_mf_components.all;
0038
0039 -- for 80MHz input-register - HB111105
0040 LIBRARY lpm;
0041 USE lpm.lpm_components.ALL;
0042
0043 USE work.cond_chip_pkg.ALL;
0044 USE work.def_val_pkg.ALL;
0045 USE work.algo_components.ALL;
0046 USE work.calo_condition_pkg.ALL;
0047 USE work.muon_condition_pkg.ALL;
0048 USE work.jc_esums_pkg.ALL;
0049 USE work.basics_pkg.ALL;
0050 USE work.vme_pkg.ALL;
0051
0052 ENTITY cond_chip IS
0053 PORT(
0054 CLK40 : IN STD_LOGIC;
0055 CLK80 : IN STD_LOGIC;
0056 CA113 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0057 CA124 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0058 CA213 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0059 CA224 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0060 CA313 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0061 CA324 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0062 CA413 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0063 CA424 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0064 CA513 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0065 CA524 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0066 CA613 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0067 CA624 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0068 CA713 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0069 CA724 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0070 CA813 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0071 CA824 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0072 CA913 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0073 CA924 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0074 CA1013 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0075 CA1024 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
0076 MU1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
0077 MU3 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
0078 ENCOND : IN STD_LOGIC;
0079 ENALGO : IN STD_LOGIC;
0080 WRCOND : IN STD_LOGIC;
0081 BCRES : IN STD_LOGIC;
0082 L1A : IN STD_LOGIC;
0083 L1RESET : IN STD_LOGIC;
0084 CLKLKEN : IN STD_LOGIC;
0085 ADDR : IN STD_LOGIC_VECTOR(21 DOWNTO 1);
0086 ADDR_0_SIM : IN STD_LOGIC; -- for quartus simulator
0087 VDATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
0088 RESERVEVME : OUT STD_LOGIC;
0089 RESERVE1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
0090 RESERVE2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
0091 RESERVE3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
0092 TEST0 : OUT STD_LOGIC;
0093 TEST1 : OUT STD_LOGIC;
0094 TEST2 : OUT STD_LOGIC;
0095 TEST3 : OUT STD_LOGIC;
0096 CLKLOCKED : OUT STD_LOGIC;
0097 STAT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
0098 NDTACK : OUT STD_LOGIC;
0099 ALGOSTROB : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
0100 ALGO : OUT STD_LOGIC_VECTOR(95 DOWNTO 0));
0101 END cond_chip;
0102 ARCHITECTURE rtl OF cond_chip IS
0103 -- *********************************************************
0104 -- NEW signals for rw-registers with dtack
0105 CONSTANT dtack_inst : boolean := true;
0106 SIGNAL reset: STD_LOGIC := '0';
0107 SIGNAL ENCOND_int: STD_LOGIC;
0108 -- dtack-signals for ieg
0109 SIGNAL dtack_ieg_1_s : STD_LOGIC_VECTOR(nr_ieg_1_s DOWNTO 0);
0110 SIGNAL dtack_ieg_2_s : STD_LOGIC_VECTOR(nr_ieg_2_s DOWNTO 0);
0111 SIGNAL dtack_ieg_2_wsc : STD_LOGIC_VECTOR(nr_ieg_2_wsc DOWNTO 0);
0112 SIGNAL dtack_ieg_4 : STD_LOGIC_VECTOR(nr_ieg_4 DOWNTO 0);
0113 -- dtack-signals for eg
0114 SIGNAL dtack_eg_1_s : STD_LOGIC_VECTOR(nr_eg_1_s DOWNTO 0);
0115 SIGNAL dtack_eg_2_s : STD_LOGIC_VECTOR(nr_eg_2_s DOWNTO 0);
0116 SIGNAL dtack_eg_2_wsc : STD_LOGIC_VECTOR(nr_eg_2_wsc DOWNTO 0);
0117 SIGNAL dtack_eg_4 : STD_LOGIC_VECTOR(nr_eg_4 DOWNTO 0);
0118 -- dtack-signals for jet
0119 SIGNAL dtack_jet_1_s : STD_LOGIC_VECTOR(nr_jet_1_s DOWNTO 0);
0120 SIGNAL dtack_jet_2_s : STD_LOGIC_VECTOR(nr_jet_2_s DOWNTO 0);
0121 SIGNAL dtack_jet_2_wsc : STD_LOGIC_VECTOR(nr_jet_2_wsc DOWNTO 0);
0122 SIGNAL dtack_jet_4 : STD_LOGIC_VECTOR(nr_jet_4 DOWNTO 0);
0123 -- dtack-signals for fwdjet
0124 SIGNAL dtack_fwdjet_1_s : STD_LOGIC_VECTOR(nr_fwdjet_1_s DOWNTO 0);
0125 SIGNAL dtack_fwdjet_2_s : STD_LOGIC_VECTOR(nr_fwdjet_2_s DOWNTO 0);
0126 SIGNAL dtack_fwdjet_2_wsc : STD_LOGIC_VECTOR(nr_fwdjet_2_wsc DOWNTO 0);
0127 SIGNAL dtack_fwdjet_4 : STD_LOGIC_VECTOR(nr_fwdjet_4 DOWNTO 0);
0128 -- dtack-signals for tau
0129 SIGNAL dtack_tau_1_s : STD_LOGIC_VECTOR(nr_tau_1_s DOWNTO 0);
0130 SIGNAL dtack_tau_2_s : STD_LOGIC_VECTOR(nr_tau_2_s DOWNTO 0);
0131 SIGNAL dtack_tau_2_wsc : STD_LOGIC_VECTOR(nr_tau_2_wsc DOWNTO 0);
0132 SIGNAL dtack_tau_4 : STD_LOGIC_VECTOR(nr_tau_4 DOWNTO 0);
0133 -- dtack-signals for muons
0134 SIGNAL dtack_muon_1_s : STD_LOGIC_VECTOR(nr_muon_1_s DOWNTO 0);
0135 SIGNAL dtack_muon_2_s : STD_LOGIC_VECTOR(nr_muon_2_s DOWNTO 0);
0136 SIGNAL dtack_muon_2_wsc : STD_LOGIC_VECTOR(nr_muon_2_wsc DOWNTO 0);
0137 SIGNAL dtack_muon_3 : STD_LOGIC_VECTOR(nr_muon_3 DOWNTO 0);
0138 SIGNAL dtack_muon_4 : STD_LOGIC_VECTOR(nr_muon_4 DOWNTO 0);
0139 -- dtack-signals for esums
0140 SIGNAL dtack_jet_cnts_0 : STD_LOGIC_VECTOR(nr_jet_cnts_0_cond DOWNTO 0);
0141 SIGNAL dtack_jet_cnts_1 : STD_LOGIC_VECTOR(nr_jet_cnts_1_cond DOWNTO 0);
0142 SIGNAL dtack_jet_cnts_2 : STD_LOGIC_VECTOR(nr_jet_cnts_2_cond DOWNTO 0);
0143 SIGNAL dtack_jet_cnts_3 : STD_LOGIC_VECTOR(nr_jet_cnts_3_cond DOWNTO 0);
0144 SIGNAL dtack_jet_cnts_4 : STD_LOGIC_VECTOR(nr_jet_cnts_4_cond DOWNTO 0);
0145 SIGNAL dtack_jet_cnts_5 : STD_LOGIC_VECTOR(nr_jet_cnts_5_cond DOWNTO 0);
0146 SIGNAL dtack_jet_cnts_6 : STD_LOGIC_VECTOR(nr_jet_cnts_6_cond DOWNTO 0);
0147 SIGNAL dtack_jet_cnts_7 : STD_LOGIC_VECTOR(nr_jet_cnts_7_cond DOWNTO 0);
0148 SIGNAL dtack_jet_cnts_8 : STD_LOGIC_VECTOR(nr_jet_cnts_8_cond DOWNTO 0);
0149 SIGNAL dtack_jet_cnts_9 : STD_LOGIC_VECTOR(nr_jet_cnts_9_cond DOWNTO 0);
0150 SIGNAL dtack_jet_cnts_10 : STD_LOGIC_VECTOR(nr_jet_cnts_10_cond DOWNTO 0);
0151 SIGNAL dtack_jet_cnts_11 : STD_LOGIC_VECTOR(nr_jet_cnts_11_cond DOWNTO 0);
0152 -- dtack-signals for esums
0153 SIGNAL dtack_ett : STD_LOGIC_VECTOR(nr_ett_cond DOWNTO 0);
0154 SIGNAL dtack_etm : STD_LOGIC_VECTOR(nr_etm_cond DOWNTO 0);
0155 SIGNAL dtack_htt : STD_LOGIC_VECTOR(nr_htt_cond DOWNTO 0);
0156 -- *********************************************************
0157 -- address signals
0158 SIGNAL addr_cond: STD_LOGIC_VECTOR(7 DOWNTO 0);
0159 SIGNAL addr_reg_name: STD_LOGIC_VECTOR(4 DOWNTO 0);
0160 -- 80MHz input register signals
0161 SIGNAL ca113_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0162 SIGNAL ca124_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0163 SIGNAL ca213_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0164 SIGNAL ca224_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0165 SIGNAL ca313_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0166 SIGNAL ca324_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0167 SIGNAL ca413_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0168 SIGNAL ca424_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0169 SIGNAL ca513_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0170 SIGNAL ca524_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0171 SIGNAL ca613_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0172 SIGNAL ca624_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0173 SIGNAL ca713_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0174 SIGNAL ca724_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0175 SIGNAL ca813_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0176 SIGNAL ca824_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0177 SIGNAL ca913_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0178 SIGNAL ca924_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0179 SIGNAL ca1013_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0180 SIGNAL ca1024_ioc: STD_LOGIC_VECTOR(15 DOWNTO 0);
0181 SIGNAL mu1_ioc: STD_LOGIC_VECTOR(25 DOWNTO 0);
0182 SIGNAL mu3_ioc: STD_LOGIC_VECTOR(25 DOWNTO 0);
0183 -- input_calos/input_muons register signals
0184 SIGNAL ca11_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0185 SIGNAL ca12_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0186 SIGNAL ca13_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0187 SIGNAL ca14_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0188 SIGNAL ca21_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0189 SIGNAL ca22_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0190 SIGNAL ca23_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0191 SIGNAL ca24_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0192 SIGNAL ca31_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0193 SIGNAL ca32_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0194 SIGNAL ca33_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0195 SIGNAL ca34_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0196 SIGNAL ca41_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0197 SIGNAL ca42_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0198 SIGNAL ca43_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0199 SIGNAL ca44_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0200 SIGNAL ca51_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0201 SIGNAL ca52_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0202 SIGNAL ca53_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0203 SIGNAL ca54_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0204 SIGNAL ca61_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0205 SIGNAL ca62_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0206 SIGNAL ca63_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0207 SIGNAL ca64_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0208 SIGNAL ca71_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0209 SIGNAL ca72_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0210 SIGNAL ca73_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0211 SIGNAL ca74_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0212 SIGNAL ca81_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0213 SIGNAL ca82_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0214 SIGNAL ca83_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0215 SIGNAL ca84_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0216 SIGNAL ca91_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0217 SIGNAL ca92_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0218 SIGNAL ca93_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0219 SIGNAL ca94_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0220 SIGNAL ca101_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0221 SIGNAL ca102_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0222 SIGNAL ca103_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0223 SIGNAL ca104_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
0224 SIGNAL mu1_reg: STD_LOGIC_VECTOR(25 DOWNTO 0);
0225 SIGNAL mu2_reg: STD_LOGIC_VECTOR(25 DOWNTO 0);
0226 SIGNAL mu3_reg: STD_LOGIC_VECTOR(25 DOWNTO 0);
0227 SIGNAL mu4_reg: STD_LOGIC_VECTOR(25 DOWNTO 0);
0228 -- particle enable signals
0229 SIGNAL ieg_en : STD_LOGIC;
0230 SIGNAL eg_en : STD_LOGIC;
0231 SIGNAL jet_en : STD_LOGIC;
0232 SIGNAL tau_en : STD_LOGIC;
0233 SIGNAL fwdjet_en : STD_LOGIC;
0234 SIGNAL muon_en : STD_LOGIC;
0235 -- IEG condition enable signals
0236 SIGNAL en_ieg_4: STD_LOGIC;
0237 SIGNAL en_ieg_2_s: STD_LOGIC;
0238 SIGNAL en_ieg_2_wsc: STD_LOGIC;
0239 SIGNAL en_ieg_1_s: STD_LOGIC;
0240 -- EG condition enable signals
0241 SIGNAL en_eg_4: STD_LOGIC;
0242 SIGNAL en_eg_2_s: STD_LOGIC;
0243 SIGNAL en_eg_2_wsc: STD_LOGIC;
0244 SIGNAL en_eg_1_s: STD_LOGIC;
0245 -- JET condition enable signals
0246 SIGNAL en_jet_4: STD_LOGIC;
0247 SIGNAL en_jet_2_s: STD_LOGIC;
0248 SIGNAL en_jet_2_wsc: STD_LOGIC;
0249 SIGNAL en_jet_1_s: STD_LOGIC;
0250 -- TAU condition enable signals
0251 SIGNAL en_tau_4: STD_LOGIC;
0252 SIGNAL en_tau_2_s: STD_LOGIC;
0253 SIGNAL en_tau_2_wsc: STD_LOGIC;
0254 SIGNAL en_tau_1_s: STD_LOGIC;
0255 -- FWDJET condition enable signals
0256 SIGNAL en_fwdjet_4: STD_LOGIC;
0257 SIGNAL en_fwdjet_2_s: STD_LOGIC;
0258 SIGNAL en_fwdjet_2_wsc: STD_LOGIC;
0259 SIGNAL en_fwdjet_1_s: STD_LOGIC;
0260 -- jet counts condition enable signals
0261 SIGNAL en_jet_cnts_0, en_jet_cnts_1, en_jet_cnts_2: STD_LOGIC;
0262 SIGNAL en_jet_cnts_3, en_jet_cnts_4, en_jet_cnts_5: STD_LOGIC;
0263 SIGNAL en_jet_cnts_6, en_jet_cnts_7, en_jet_cnts_8: STD_LOGIC;
0264 SIGNAL en_jet_cnts_9, en_jet_cnts_10, en_jet_cnts_11: STD_LOGIC;
0265 -- e_sums condition enable signals
0266 SIGNAL en_ett_cond: STD_LOGIC;
0267 SIGNAL en_etm_cond: STD_LOGIC;
0268 SIGNAL en_htt_cond: STD_LOGIC;
0269 -- MUON condition enable signals
0270 SIGNAL en_muon_4: STD_LOGIC;
0271 SIGNAL en_muon_2_s: STD_LOGIC;
0272 SIGNAL en_muon_2_wsc: STD_LOGIC;
0273 SIGNAL en_muon_1_s: STD_LOGIC;
0274 SIGNAL en_muon_3: STD_LOGIC;
0275 -- outputs of inputregisters IEG
0276 SIGNAL reg_ieg_et_1: STD_LOGIC_VECTOR(5 DOWNTO 0);
0277 SIGNAL reg_ieg_et_2: STD_LOGIC_VECTOR(5 DOWNTO 0);
0278 SIGNAL reg_ieg_et_3: STD_LOGIC_VECTOR(5 DOWNTO 0);
0279 SIGNAL reg_ieg_et_4: STD_LOGIC_VECTOR(5 DOWNTO 0);
0280 SIGNAL reg_ieg_eta_1: STD_LOGIC_VECTOR(3 DOWNTO 0);
0281 SIGNAL reg_ieg_eta_2: STD_LOGIC_VECTOR(3 DOWNTO 0);
0282 SIGNAL reg_ieg_eta_3: STD_LOGIC_VECTOR(3 DOWNTO 0);
0283 SIGNAL reg_ieg_eta_4: STD_LOGIC_VECTOR(3 DOWNTO 0);
0284 SIGNAL reg_ieg_phi_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0285 SIGNAL reg_ieg_phi_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0286 SIGNAL reg_ieg_phi_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0287 SIGNAL reg_ieg_phi_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0288 SIGNAL reg_ieg_sync_1: STD_LOGIC;
0289 SIGNAL reg_ieg_sync_2: STD_LOGIC;
0290 SIGNAL reg_ieg_sync_3: STD_LOGIC;
0291 SIGNAL reg_ieg_sync_4: STD_LOGIC;
0292 -- outputs of inputregisters EG
0293 SIGNAL reg_eg_et_1: STD_LOGIC_VECTOR(5 DOWNTO 0);
0294 SIGNAL reg_eg_et_2: STD_LOGIC_VECTOR(5 DOWNTO 0);
0295 SIGNAL reg_eg_et_3: STD_LOGIC_VECTOR(5 DOWNTO 0);
0296 SIGNAL reg_eg_et_4: STD_LOGIC_VECTOR(5 DOWNTO 0);
0297 SIGNAL reg_eg_eta_1: STD_LOGIC_VECTOR(3 DOWNTO 0);
0298 SIGNAL reg_eg_eta_2: STD_LOGIC_VECTOR(3 DOWNTO 0);
0299 SIGNAL reg_eg_eta_3: STD_LOGIC_VECTOR(3 DOWNTO 0);
0300 SIGNAL reg_eg_eta_4: STD_LOGIC_VECTOR(3 DOWNTO 0);
0301 SIGNAL reg_eg_phi_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0302 SIGNAL reg_eg_phi_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0303 SIGNAL reg_eg_phi_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0304 SIGNAL reg_eg_phi_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0305 SIGNAL reg_eg_sync_1: STD_LOGIC;
0306 SIGNAL reg_eg_sync_2: STD_LOGIC;
0307 SIGNAL reg_eg_sync_3: STD_LOGIC;
0308 SIGNAL reg_eg_sync_4: STD_LOGIC;
0309 -- outputs of inputregisters JET
0310 SIGNAL reg_jet_et_1: STD_LOGIC_VECTOR(5 DOWNTO 0);
0311 SIGNAL reg_jet_et_2: STD_LOGIC_VECTOR(5 DOWNTO 0);
0312 SIGNAL reg_jet_et_3: STD_LOGIC_VECTOR(5 DOWNTO 0);
0313 SIGNAL reg_jet_et_4: STD_LOGIC_VECTOR(5 DOWNTO 0);
0314 SIGNAL reg_jet_eta_1: STD_LOGIC_VECTOR(3 DOWNTO 0);
0315 SIGNAL reg_jet_eta_2: STD_LOGIC_VECTOR(3 DOWNTO 0);
0316 SIGNAL reg_jet_eta_3: STD_LOGIC_VECTOR(3 DOWNTO 0);
0317 SIGNAL reg_jet_eta_4: STD_LOGIC_VECTOR(3 DOWNTO 0);
0318 SIGNAL reg_jet_phi_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0319 SIGNAL reg_jet_phi_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0320 SIGNAL reg_jet_phi_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0321 SIGNAL reg_jet_phi_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0322 SIGNAL reg_jet_sync_1: STD_LOGIC;
0323 SIGNAL reg_jet_sync_2: STD_LOGIC;
0324 SIGNAL reg_jet_sync_3: STD_LOGIC;
0325 SIGNAL reg_jet_sync_4: STD_LOGIC;
0326 -- outputs of inputregisters FWDJET
0327 SIGNAL reg_fwdjet_et_1: STD_LOGIC_VECTOR(5 DOWNTO 0);
0328 SIGNAL reg_fwdjet_et_2: STD_LOGIC_VECTOR(5 DOWNTO 0);
0329 SIGNAL reg_fwdjet_et_3: STD_LOGIC_VECTOR(5 DOWNTO 0);
0330 SIGNAL reg_fwdjet_et_4: STD_LOGIC_VECTOR(5 DOWNTO 0);
0331 SIGNAL reg_fwdjet_eta_1: STD_LOGIC_VECTOR(3 DOWNTO 0);
0332 SIGNAL reg_fwdjet_eta_2: STD_LOGIC_VECTOR(3 DOWNTO 0);
0333 SIGNAL reg_fwdjet_eta_3: STD_LOGIC_VECTOR(3 DOWNTO 0);
0334 SIGNAL reg_fwdjet_eta_4: STD_LOGIC_VECTOR(3 DOWNTO 0);
0335 SIGNAL reg_fwdjet_phi_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0336 SIGNAL reg_fwdjet_phi_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0337 SIGNAL reg_fwdjet_phi_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0338 SIGNAL reg_fwdjet_phi_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0339 SIGNAL reg_fwdjet_sync_1: STD_LOGIC;
0340 SIGNAL reg_fwdjet_sync_2: STD_LOGIC;
0341 SIGNAL reg_fwdjet_sync_3: STD_LOGIC;
0342 SIGNAL reg_fwdjet_sync_4: STD_LOGIC;
0343 -- outputs of inputregisters TAU
0344 SIGNAL reg_tau_et_1: STD_LOGIC_VECTOR(5 DOWNTO 0);
0345 SIGNAL reg_tau_et_2: STD_LOGIC_VECTOR(5 DOWNTO 0);
0346 SIGNAL reg_tau_et_3: STD_LOGIC_VECTOR(5 DOWNTO 0);
0347 SIGNAL reg_tau_et_4: STD_LOGIC_VECTOR(5 DOWNTO 0);
0348 SIGNAL reg_tau_eta_1: STD_LOGIC_VECTOR(3 DOWNTO 0);
0349 SIGNAL reg_tau_eta_2: STD_LOGIC_VECTOR(3 DOWNTO 0);
0350 SIGNAL reg_tau_eta_3: STD_LOGIC_VECTOR(3 DOWNTO 0);
0351 SIGNAL reg_tau_eta_4: STD_LOGIC_VECTOR(3 DOWNTO 0);
0352 SIGNAL reg_tau_phi_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0353 SIGNAL reg_tau_phi_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0354 SIGNAL reg_tau_phi_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0355 SIGNAL reg_tau_phi_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0356 SIGNAL reg_tau_sync_1: STD_LOGIC;
0357 SIGNAL reg_tau_sync_2: STD_LOGIC;
0358 SIGNAL reg_tau_sync_3: STD_LOGIC;
0359 SIGNAL reg_tau_sync_4: STD_LOGIC;
0360 -- outputs of inputregisters "e_sums"
0361 SIGNAL reg_ett : STD_LOGIC_VECTOR(12 DOWNTO 0);
0362 SIGNAL reg_htt : STD_LOGIC_VECTOR(12 DOWNTO 0);
0363 SIGNAL reg_etm : STD_LOGIC_VECTOR(12 DOWNTO 0);
0364 SIGNAL reg_etm_phi : STD_LOGIC_VECTOR(6 DOWNTO 0);
0365 SIGNAL reg_esums_sync_1: STD_LOGIC;
0366 SIGNAL reg_esums_sync_2: STD_LOGIC;
0367 SIGNAL reg_esums_sync_3: STD_LOGIC;
0368 SIGNAL reg_esums_sync_4: STD_LOGIC;
0369 -- outputs of inputregisters "jet-counters"
0370 SIGNAL reg_jet_cnts_0: STD_LOGIC_VECTOR(4 DOWNTO 0);
0371 SIGNAL reg_jet_cnts_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0372 SIGNAL reg_jet_cnts_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0373 SIGNAL reg_jet_cnts_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0374 SIGNAL reg_jet_cnts_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0375 SIGNAL reg_jet_cnts_5: STD_LOGIC_VECTOR(4 DOWNTO 0);
0376 SIGNAL reg_jet_cnts_6: STD_LOGIC_VECTOR(4 DOWNTO 0);
0377 SIGNAL reg_jet_cnts_7: STD_LOGIC_VECTOR(4 DOWNTO 0);
0378 SIGNAL reg_jet_cnts_8: STD_LOGIC_VECTOR(4 DOWNTO 0);
0379 SIGNAL reg_jet_cnts_9: STD_LOGIC_VECTOR(4 DOWNTO 0);
0380 SIGNAL reg_jet_cnts_10: STD_LOGIC_VECTOR(4 DOWNTO 0);
0381 SIGNAL reg_jet_cnts_11: STD_LOGIC_VECTOR(4 DOWNTO 0);
0382 SIGNAL reg_jet_cnts_sync_1: STD_LOGIC;
0383 SIGNAL reg_jet_cnts_sync_2: STD_LOGIC;
0384 SIGNAL reg_jet_cnts_sync_3: STD_LOGIC;
0385 SIGNAL reg_jet_cnts_sync_4: STD_LOGIC;
0386 -- outputs of inputregisters MUON
0387 SIGNAL reg_muon_pt_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
0388 SIGNAL reg_muon_pt_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
0389 SIGNAL reg_muon_pt_3: STD_LOGIC_VECTOR(4 DOWNTO 0);
0390 SIGNAL reg_muon_pt_4: STD_LOGIC_VECTOR(4 DOWNTO 0);
0391 SIGNAL reg_muon_eta_1: STD_LOGIC_VECTOR(5 DOWNTO 0);
0392 SIGNAL reg_muon_eta_2: STD_LOGIC_VECTOR(5 DOWNTO 0);
0393 SIGNAL reg_muon_eta_3: STD_LOGIC_VECTOR(5 DOWNTO 0);
0394 SIGNAL reg_muon_eta_4: STD_LOGIC_VECTOR(5 DOWNTO 0);
0395 SIGNAL reg_muon_phi_1: STD_LOGIC_VECTOR(7 DOWNTO 0);
0396 SIGNAL reg_muon_phi_2: STD_LOGIC_VECTOR(7 DOWNTO 0);
0397 SIGNAL reg_muon_phi_3: STD_LOGIC_VECTOR(7 DOWNTO 0);
0398 SIGNAL reg_muon_phi_4: STD_LOGIC_VECTOR(7 DOWNTO 0);
0399 SIGNAL reg_muon_qual_1: STD_LOGIC_VECTOR(2 DOWNTO 0);
0400 SIGNAL reg_muon_qual_2: STD_LOGIC_VECTOR(2 DOWNTO 0);
0401 SIGNAL reg_muon_qual_3: STD_LOGIC_VECTOR(2 DOWNTO 0);
0402 SIGNAL reg_muon_qual_4: STD_LOGIC_VECTOR(2 DOWNTO 0);
0403 SIGNAL reg_muon_iso_1: STD_LOGIC;
0404 SIGNAL reg_muon_iso_2: STD_LOGIC;
0405 SIGNAL reg_muon_iso_3: STD_LOGIC;
0406 SIGNAL reg_muon_iso_4: STD_LOGIC;
0407 SIGNAL reg_muon_mip_1: STD_LOGIC;
0408 SIGNAL reg_muon_mip_2: STD_LOGIC;
0409 SIGNAL reg_muon_mip_3: STD_LOGIC;
0410 SIGNAL reg_muon_mip_4: STD_LOGIC;
0411 SIGNAL reg_muon_sy_0_1: STD_LOGIC;
0412 SIGNAL reg_muon_sy_0_2: STD_LOGIC;
0413 SIGNAL reg_muon_sy_0_3: STD_LOGIC;
0414 SIGNAL reg_muon_sy_0_4: STD_LOGIC;
0415 SIGNAL reg_muon_sy_1_1: STD_LOGIC;
0416 SIGNAL reg_muon_sy_1_2: STD_LOGIC;
0417 SIGNAL reg_muon_sy_1_3: STD_LOGIC;
0418 SIGNAL reg_muon_sy_1_4: STD_LOGIC;
0419 -- condition outputs
0420 -- calos
0421 SIGNAL ieg_4: STD_LOGIC_VECTOR(nr_ieg_4 DOWNTO 0);
0422 SIGNAL ieg_2_s: STD_LOGIC_VECTOR(nr_ieg_2_s DOWNTO 0);
0423 SIGNAL ieg_2_wsc: STD_LOGIC_VECTOR(nr_ieg_2_wsc DOWNTO 0);
0424 SIGNAL ieg_1_s: STD_LOGIC_VECTOR(nr_ieg_1_s DOWNTO 0);
0425 SIGNAL eg_4: STD_LOGIC_VECTOR(nr_eg_4 DOWNTO 0);
0426 SIGNAL eg_2_s: STD_LOGIC_VECTOR(nr_eg_2_s DOWNTO 0);
0427 SIGNAL eg_2_wsc: STD_LOGIC_VECTOR(nr_eg_2_wsc DOWNTO 0);
0428 SIGNAL eg_1_s: STD_LOGIC_VECTOR(nr_eg_1_s DOWNTO 0);
0429 SIGNAL jet_4: STD_LOGIC_VECTOR(nr_jet_4 DOWNTO 0);
0430 SIGNAL jet_2_s: STD_LOGIC_VECTOR(nr_jet_2_s DOWNTO 0);
0431 SIGNAL jet_2_wsc: STD_LOGIC_VECTOR(nr_jet_2_wsc DOWNTO 0);
0432 SIGNAL jet_1_s: STD_LOGIC_VECTOR(nr_jet_1_s DOWNTO 0);
0433 SIGNAL tau_4: STD_LOGIC_VECTOR(nr_tau_4 DOWNTO 0);
0434 SIGNAL tau_2_s: STD_LOGIC_VECTOR(nr_tau_2_s DOWNTO 0);
0435 SIGNAL tau_2_wsc: STD_LOGIC_VECTOR(nr_tau_2_wsc DOWNTO 0);
0436 SIGNAL tau_1_s: STD_LOGIC_VECTOR(nr_tau_1_s DOWNTO 0);
0437 SIGNAL fwdjet_4: STD_LOGIC_VECTOR(nr_fwdjet_4 DOWNTO 0);
0438 SIGNAL fwdjet_2_s: STD_LOGIC_VECTOR(nr_fwdjet_2_s DOWNTO 0);
0439 SIGNAL fwdjet_2_wsc: STD_LOGIC_VECTOR(nr_fwdjet_2_wsc DOWNTO 0);
0440 SIGNAL fwdjet_1_s: STD_LOGIC_VECTOR(nr_fwdjet_1_s DOWNTO 0);
0441 -- muons
0442 SIGNAL muon_4: STD_LOGIC_VECTOR(nr_muon_4 DOWNTO 0);
0443 SIGNAL muon_2_s: STD_LOGIC_VECTOR(nr_muon_2_s DOWNTO 0);
0444 SIGNAL muon_2_wsc: STD_LOGIC_VECTOR(nr_muon_2_wsc DOWNTO 0);
0445 SIGNAL muon_1_s: STD_LOGIC_VECTOR(nr_muon_1_s DOWNTO 0);
0446 SIGNAL muon_3: STD_LOGIC_VECTOR(nr_muon_3 DOWNTO 0);
0447 -- jet-counters
0448 SIGNAL jet_cnts_0_cond: STD_LOGIC_VECTOR(nr_jet_cnts_0_cond DOWNTO 0);
0449 SIGNAL jet_cnts_1_cond: STD_LOGIC_VECTOR(nr_jet_cnts_1_cond DOWNTO 0);
0450 SIGNAL jet_cnts_2_cond: STD_LOGIC_VECTOR(nr_jet_cnts_2_cond DOWNTO 0);
0451 SIGNAL jet_cnts_3_cond: STD_LOGIC_VECTOR(nr_jet_cnts_3_cond DOWNTO 0);
0452 SIGNAL jet_cnts_4_cond: STD_LOGIC_VECTOR(nr_jet_cnts_4_cond DOWNTO 0);
0453 SIGNAL jet_cnts_5_cond: STD_LOGIC_VECTOR(nr_jet_cnts_5_cond DOWNTO 0);
0454 SIGNAL jet_cnts_6_cond: STD_LOGIC_VECTOR(nr_jet_cnts_6_cond DOWNTO 0);
0455 SIGNAL jet_cnts_7_cond: STD_LOGIC_VECTOR(nr_jet_cnts_7_cond DOWNTO 0);
0456 SIGNAL jet_cnts_8_cond: STD_LOGIC_VECTOR(nr_jet_cnts_8_cond DOWNTO 0);
0457 SIGNAL jet_cnts_9_cond: STD_LOGIC_VECTOR(nr_jet_cnts_9_cond DOWNTO 0);
0458 SIGNAL jet_cnts_10_cond: STD_LOGIC_VECTOR(nr_jet_cnts_10_cond DOWNTO 0);
0459 SIGNAL jet_cnts_11_cond: STD_LOGIC_VECTOR(nr_jet_cnts_11_cond DOWNTO 0);
0460 -- e_sums
0461 SIGNAL ett_cond: STD_LOGIC_VECTOR(nr_ett_cond DOWNTO 0);
0462 SIGNAL etm_cond: STD_LOGIC_VECTOR(nr_etm_cond DOWNTO 0);
0463 SIGNAL htt_cond: STD_LOGIC_VECTOR(nr_htt_cond DOWNTO 0);
0464 -- inputs of pre-algo outputregister
0465 SIGNAL algo_mux_in: STD_LOGIC_VECTOR(95 DOWNTO 0);
0466 SIGNAL algo_cond_mem: STD_LOGIC_VECTOR(95 DOWNTO 0);
0467 SIGNAL ALGO_OUT_REG_IN: STD_LOGIC_VECTOR(95 DOWNTO 0);
0468 SIGNAL ALGOSTROB_reg: STD_LOGIC_VECTOR(2 DOWNTO 0);
0469 -- internal clock name
0470 SIGNAL clk_inp : STD_LOGIC;
0471 SIGNAL clk_cond : STD_LOGIC;
0472 SIGNAL clk_algo : STD_LOGIC;
0473 -- DTACK/BERR signals
0474 SIGNAL dtack_calo_muon: STD_LOGIC;
0475 SIGNAL dtack_int: STD_LOGIC;
0476 SIGNAL ndtack_int: STD_LOGIC;
0477 SIGNAL DTACK_COND_MEM: STD_LOGIC;
0478 SIGNAL dtack_chip_id: STD_LOGIC;
0479 SIGNAL dtack_mux: STD_LOGIC;
0480 -- muon charge logic signals
0481 SIGNAL sync_word : STD_LOGIC;
0482 -- for m_cond_1_s
0483 SIGNAL pos_lut_1, pos_lut_2, pos_lut_3, pos_lut_4 : STD_LOGIC;
0484 SIGNAL neg_lut_1, neg_lut_2, neg_lut_3, neg_lut_4 : STD_LOGIC;
0485 -- for m_cond_2_s and m_cond_2_wsc
0486 SIGNAL eq_lut_12, eq_lut_13, eq_lut_14 : STD_LOGIC;
0487 SIGNAL eq_lut_23, eq_lut_24, eq_lut_34 : STD_LOGIC;
0488 SIGNAL neq_lut_12, neq_lut_13, neq_lut_14 : STD_LOGIC;
0489 SIGNAL neq_lut_23, neq_lut_24, neq_lut_34 : STD_LOGIC;
0490 -- for m_cond_3
0491 SIGNAL eq_lut_123, eq_lut_124, eq_lut_134, eq_lut_234 : STD_LOGIC;
0492 SIGNAL neq_lut_123, neq_lut_124, neq_lut_134, neq_lut_234 : STD_LOGIC;
0493 -- for m_cond_4
0494 SIGNAL eq_lut_1234, pair_lut : STD_LOGIC;
0495 -- internal pll names
0496 SIGNAL CLK40_PLL : STD_LOGIC;
0497 SIGNAL CLK80_PLL : STD_LOGIC;
0498 SIGNAL TEST80_PLL : STD_LOGIC;
0499 SIGNAL pll_locked : STD_LOGIC;
0500 BEGIN
0501 -- ************* DEFINITIONS *******************************
0502 -- addresses
0503 addr_cond(7 DOWNTO 2) <= addr(13 DOWNTO 8);
0504 addr_cond(1 DOWNTO 0) <= addr(2 DOWNTO 1);
0505 addr_reg_name(4 DOWNTO 0) <= addr(7 DOWNTO 3);
0506 -- clocks
0507 clk_inp <= CLK40_PLL;
0508 clk_cond <= CLK40_PLL;
0509 clk_algo <= CLK40_PLL;
0510 -- Testoutputs
0511 TEST0 <= dtack_jet_cnts_8(1-1);
0512 --TEST0 <= CLK40;
0513 TEST1 <= TEST80_PLL;
0514 TEST2 <= pll_locked;
0515 TEST3 <= CLK80;
0516 -- status outputs, not used now !!!
0517 STAT(0) <= '0';
0518 STAT(1) <= '0';
0519 -- PLL "locked" output
0520 CLKLOCKED <= pll_locked;
0521 -- reserve outputs (inputs) to VME- and REC-chips, not used now !!!
0522 RESERVEVME <= '0';
0523 RESERVE1 <= X"0000";
0524 RESERVE2 <= X"0000";
0525 RESERVE3 <= X"0000";
0526 -- ************* PLL SECTION *******************************
0527 -- HB 111105
0528 -- altclklock einfacher, als altpll !!!
0529 -- simulation schaut gut aus !!!
0530 -- CLK40_PLL eingebaut, damit setup für calos_ioc und muons_ioc passt - HB010206 !!!
0531 -- INCLOCK_PERIOD eingebaut für timing constraints - HB150208 !!!
0532 pll_inst: altclklock
0533 GENERIC MAP(INTENDED_DEVICE_FAMILY => "STRATIX",
0534 OPERATION_MODE => "NORMAL",
0535 INCLOCK_PERIOD => INCLOCK_PERIOD, -- see cond_chip_pkg.vhd !!!
0536 VALID_LOCK_MULTIPLIER => 1,
0537 CLOCK0_BOOST => 2, CLOCK1_BOOST => 2, CLOCK2_BOOST => 1)
0538 PORT MAP(
0539 inclock => CLK40,
0540 clock0 => CLK80_PLL,
0541 clock1 => TEST80_PLL,
0542 clock2 => CLK40_PLL,
0543 locked => pll_locked);
0544
0545 -- ************* VME SECTION *******************************
0546 -- REMARK: ENCOND for a write-cycle is made with DSPULS (25ns !!!) in VME-chip (V1004)
0547 -- REMARK: ENCOND for a read-cycle is made with DSSYNC in VME-chip (V1004)
0548 -- ENCOND_int is generated for proper use in rw-registers
0549 call_encond_sync: bit_reg
0550 PORT MAP(clk_inp, ENCOND,
0551 ENCOND_int);
0552
0553 -- decoders for VME-registers
0554 call_calo_dec: calo_decoder
0555 GENERIC MAP (rd_reg_inst)
0556 PORT MAP(
0557 ENCOND_int, WRCOND, addr(21 DOWNTO 14),
0558 ieg_en, eg_en, jet_en, tau_en, fwdjet_en,
0559 en_ieg_4, en_ieg_2_s, en_ieg_2_wsc, en_ieg_1_s,
0560 en_eg_4, en_eg_2_s, en_eg_2_wsc, en_eg_1_s,
0561 en_jet_4, en_jet_2_s, en_jet_2_wsc, en_jet_1_s,
0562 en_tau_4, en_tau_2_s, en_tau_2_wsc, en_tau_1_s,
0563 en_fwdjet_4, en_fwdjet_2_s, en_fwdjet_2_wsc,
0564 en_fwdjet_1_s);
0565
0566 call_muon_dec: muon_decoder
0567 GENERIC MAP (rd_reg_inst)
0568 PORT MAP(
0569 ENCOND_int, WRCOND, addr(21 DOWNTO 14),
0570 en_muon_4, en_muon_2_s, en_muon_2_wsc,
0571 en_muon_1_s, en_muon_3);
0572
0573 call_jc_es_dec: jc_es_decoder
0574 GENERIC MAP (rd_reg_inst)
0575 PORT MAP(
0576 ENCOND_int, WRCOND, addr(21 DOWNTO 14),
0577 en_jet_cnts_0, en_jet_cnts_1, en_jet_cnts_2,
0578 en_jet_cnts_3, en_jet_cnts_4, en_jet_cnts_5,
0579 en_jet_cnts_6, en_jet_cnts_7, en_jet_cnts_8,
0580 en_jet_cnts_9, en_jet_cnts_10, en_jet_cnts_11,
0581 en_ett_cond, en_etm_cond, en_htt_cond);
0582
0583 -- chip_id- and version-registers (read only)
0584 call_chip_id_version: chip_id_version
0585 GENERIC MAP(chip_id, version)
0586 PORT MAP(
0587 ENCOND_int, WRCOND, ADDR(21 DOWNTO 1), VDATA(7 DOWNTO 0),
0588 DTACK_chip_id);
0589
0590 -- ndtack_int logic from register
0591 call_dtack_inst:
0592 IF dtack_inst = true GENERATE
0593 call_dtack_calos_muon_or: dtack_calos_muon_or
0594 GENERIC MAP (
0595 nr_ieg_4, nr_ieg_2_s, nr_ieg_2_wsc, nr_ieg_1_s,
0596 nr_eg_4, nr_eg_2_s, nr_eg_2_wsc, nr_eg_1_s,
0597 nr_jet_4, nr_jet_2_s, nr_jet_2_wsc, nr_jet_1_s,
0598 nr_tau_4, nr_tau_2_s, nr_tau_2_wsc, nr_tau_1_s,
0599 nr_fwdjet_4, nr_fwdjet_2_s, nr_fwdjet_2_wsc, nr_fwdjet_1_s,
0600 nr_muon_4, nr_muon_2_s, nr_muon_2_wsc, nr_muon_1_s, nr_muon_3,
0601 nr_jet_cnts_0_cond, nr_jet_cnts_1_cond, nr_jet_cnts_2_cond,
0602 nr_jet_cnts_3_cond, nr_jet_cnts_4_cond, nr_jet_cnts_5_cond,
0603 nr_jet_cnts_6_cond, nr_jet_cnts_7_cond, nr_jet_cnts_8_cond,
0604 nr_jet_cnts_9_cond, nr_jet_cnts_10_cond, nr_jet_cnts_11_cond,
0605 nr_ett_cond, nr_etm_cond, nr_htt_cond)
0606 PORT MAP(
0607 dtack_ieg_1_s, dtack_ieg_2_s, dtack_ieg_2_wsc, dtack_ieg_4,
0608 dtack_eg_1_s, dtack_eg_2_s, dtack_eg_2_wsc, dtack_eg_4,
0609 dtack_jet_1_s, dtack_jet_2_s, dtack_jet_2_wsc, dtack_jet_4,
0610 dtack_tau_1_s, dtack_tau_2_s, dtack_tau_2_wsc, dtack_tau_4,
0611 dtack_fwdjet_1_s, dtack_fwdjet_2_s, dtack_fwdjet_2_wsc, dtack_fwdjet_4,
0612 dtack_muon_1_s, dtack_muon_2_s, dtack_muon_2_wsc, dtack_muon_3, dtack_muon_4,
0613 dtack_jet_cnts_0, dtack_jet_cnts_1, dtack_jet_cnts_2, dtack_jet_cnts_3,
0614 dtack_jet_cnts_4, dtack_jet_cnts_5, dtack_jet_cnts_6, dtack_jet_cnts_7,
0615 dtack_jet_cnts_8, dtack_jet_cnts_9, dtack_jet_cnts_10, dtack_jet_cnts_11,
0616 dtack_ett, dtack_etm, dtack_htt,
0617 dtack_int);
0618 END GENERATE call_dtack_inst;
0619
0620 NDTACK <= NOT (dtack_int OR dtack_chip_id OR DTACK_MUX OR DTACK_COND_MEM);
0621
0622 -- open drain outputs for NDTACK !!!
0623 --ndtack_int <= NOT (dtack_int OR dtack_chip_id OR DTACK_MUX OR DTACK_COND_MEM);
0624
0625 --open_drain_ndtack: OPNDRN
0626 -- PORT MAP(ndtack_int, NDTACK);
0627
0628 -- ********************************************************************************************************
0629 -- BEGIN OF CONDITION-ALGO-LOGIC
0630 -- ********************************************************************************************************
0631 --
0632 -- ************* INPUT DEFINITIONS *******************************
0633 -- HB 111105
0634 -- input-registers with CLK80_PLL implemented on calo- and muon-inputs
0635 -- calorimeters
0636 -- ca113 ... 80MHz data (channel 1, objects 1 and 3) from pin
0637 -- ca113_ioc ... 80MHz data (channel 1, objects 1 and 3) output of register
0638 calos_ioc_inst: calos_ioc
0639 GENERIC MAP(16)
0640 PORT MAP(CLK80_PLL,
0641 ca113, ca124, ca213, ca224, ca313, ca324,
0642 ca413, ca424, ca513, ca524, ca613, ca624,
0643 ca713, ca724, ca813, ca824, ca913, ca924,
0644 ca1013, ca1024,
0645 ca113_ioc, ca124_ioc, ca213_ioc, ca224_ioc,
0646 ca313_ioc, ca324_ioc, ca413_ioc, ca424_ioc,
0647 ca513_ioc, ca524_ioc, ca613_ioc, ca624_ioc,
0648 ca713_ioc, ca724_ioc, ca813_ioc, ca824_ioc,
0649 ca913_ioc, ca924_ioc, ca1013_ioc, ca1024_ioc);
0650 muons_ioc_inst: muons_ioc
0651 GENERIC MAP(26)
0652 PORT MAP(CLK80_PLL,
0653 mu1, mu3,
0654 mu1_ioc, mu3_ioc);
0655 -- ca41_reg ... 40MHz data, object 1 of channel 4
0656 -- ca42_reg ... 40MHz data, object 2 of channel 4
0657 ca113_in_reg: input_calos
0658 GENERIC MAP (16)
0659 PORT MAP (clk_inp,
0660 ca113_ioc, ca11_reg, ca13_reg);
0661 ca124_in_reg: input_calos
0662 GENERIC MAP (16)
0663 PORT MAP (clk_inp,
0664 ca124_ioc, ca12_reg, ca14_reg);
0665 ca213_in_reg: input_calos
0666 GENERIC MAP (16)
0667 PORT MAP (clk_inp,
0668 ca213_ioc, ca21_reg, ca23_reg);
0669 ca224_in_reg: input_calos
0670 GENERIC MAP (16)
0671 PORT MAP (clk_inp,
0672 ca224_ioc, ca22_reg, ca24_reg);
0673 ca313_in_reg: input_calos
0674 GENERIC MAP (16)
0675 PORT MAP (clk_inp,
0676 ca313_ioc, ca31_reg, ca33_reg);
0677 ca324_in_reg: input_calos
0678 GENERIC MAP (16)
0679 PORT MAP (clk_inp,
0680 ca324_ioc, ca32_reg, ca34_reg);
0681 ca413_in_reg: input_calos
0682 GENERIC MAP (16)
0683 PORT MAP (clk_inp,
0684 ca413_ioc, ca41_reg, ca43_reg);
0685 ca424_in_reg: input_calos
0686 GENERIC MAP (16)
0687 PORT MAP (clk_inp,
0688 ca424_ioc, ca42_reg, ca44_reg);
0689 ca513_in_reg: input_calos
0690 GENERIC MAP (16)
0691 PORT MAP (clk_inp,
0692 ca513_ioc, ca51_reg, ca53_reg);
0693 ca524_in_reg: input_calos
0694 GENERIC MAP (16)
0695 PORT MAP (clk_inp,
0696 ca524_ioc, ca52_reg, ca54_reg);
0697 ca613_in_reg: input_calos
0698 GENERIC MAP (16)
0699 PORT MAP (clk_inp,
0700 ca613_ioc, ca61_reg, ca63_reg);
0701 ca624_in_reg: input_calos
0702 GENERIC MAP (16)
0703 PORT MAP (clk_inp,
0704 ca624_ioc, ca62_reg, ca64_reg);
0705 ca713_in_reg: input_calos
0706 GENERIC MAP (16)
0707 PORT MAP (clk_inp,
0708 ca713_ioc, ca71_reg, ca73_reg);
0709 ca724_in_reg: input_calos
0710 GENERIC MAP (16)
0711 PORT MAP (clk_inp,
0712 ca724_ioc, ca72_reg, ca74_reg);
0713 ca813_in_reg: input_calos
0714 GENERIC MAP (16)
0715 PORT MAP (clk_inp,
0716 ca813_ioc, ca81_reg, ca83_reg);
0717 ca824_in_reg: input_calos
0718 GENERIC MAP (16)
0719 PORT MAP (clk_inp,
0720 ca824_ioc, ca82_reg, ca84_reg);
0721 ca913_in_reg: input_calos
0722 GENERIC MAP (16)
0723 PORT MAP (clk_inp,
0724 ca913_ioc, ca91_reg, ca93_reg);
0725 ca924_in_reg: input_calos
0726 GENERIC MAP (16)
0727 PORT MAP (clk_inp,
0728 ca924_ioc, ca92_reg, ca94_reg);
0729 ca1013_in_reg: input_calos
0730 GENERIC MAP (16)
0731 PORT MAP (clk_inp,
0732 ca1013_ioc, ca101_reg, ca103_reg);
0733 ca1024_in_reg: input_calos
0734 GENERIC MAP (16)
0735 PORT MAP (clk_inp,
0736 ca1024_ioc, ca102_reg, ca104_reg);
0737 -- muons
0738 mu1_in_reg: input_muons
0739 GENERIC MAP (26)
0740 PORT MAP (clk_inp,
0741 mu1_ioc, mu1_reg, mu2_reg);
0742 mu3_in_reg: input_muons
0743 GENERIC MAP (26)
0744 PORT MAP (clk_inp,
0745 mu3_ioc, mu3_reg, mu4_reg);
0746
0747 -- ************* CONDITION LOGIC *******************************
0748 -- see condition-instantiations at end of file
0749
0750 -- ************* ALGORITHM LOGIC *******************************
0751 -- logic of algo_and_or depends on definitions in def.xml, generated by gts !!!
0752
0753 call_algo_and_or: algo_and_or
0754 GENERIC MAP(
0755 nr_ieg_4, nr_ieg_2_s, nr_ieg_2_wsc, nr_ieg_1_s,
0756 nr_eg_4, nr_eg_2_s, nr_eg_2_wsc, nr_eg_1_s,
0757 nr_jet_4, nr_jet_2_s, nr_jet_2_wsc, nr_jet_1_s,
0758 nr_tau_4, nr_tau_2_s, nr_tau_2_wsc, nr_tau_1_s,
0759 nr_fwdjet_4, nr_fwdjet_2_s, nr_fwdjet_2_wsc, nr_fwdjet_1_s,
0760 nr_muon_4, nr_muon_2_s, nr_muon_2_wsc, nr_muon_1_s, nr_muon_3,
0761 nr_jet_cnts_0_cond, nr_jet_cnts_1_cond, nr_jet_cnts_2_cond,
0762 nr_jet_cnts_3_cond, nr_jet_cnts_4_cond, nr_jet_cnts_5_cond,
0763 nr_jet_cnts_6_cond, nr_jet_cnts_7_cond, nr_jet_cnts_8_cond,
0764 nr_jet_cnts_9_cond, nr_jet_cnts_10_cond, nr_jet_cnts_11_cond,
0765 nr_ett_cond, nr_etm_cond, nr_htt_cond)
0766 PORT MAP(
0767 ieg_4, ieg_2_s, ieg_2_wsc, ieg_1_s,
0768 eg_4, eg_2_s, eg_2_wsc, eg_1_s,
0769 jet_4, jet_2_s, jet_2_wsc, jet_1_s,
0770 tau_4, tau_2_s, tau_2_wsc, tau_1_s,
0771 fwdjet_4, fwdjet_2_s, fwdjet_2_wsc, fwdjet_1_s,
0772 muon_4, muon_2_s, muon_2_wsc, muon_1_s, muon_3,
0773 jet_cnts_0_cond, jet_cnts_1_cond, jet_cnts_2_cond,
0774 jet_cnts_3_cond, jet_cnts_4_cond, jet_cnts_5_cond,
0775 jet_cnts_6_cond, jet_cnts_7_cond, jet_cnts_8_cond,
0776 jet_cnts_9_cond, jet_cnts_10_cond, jet_cnts_11_cond,
0777 ett_cond, etm_cond, htt_cond,
0778 ALGOSTROB_reg, algo_mux_in);
0779
0780 -- ************* INPUT DATA MUX *******************************
0781 -- input data multiplexer part for tests
0782
0783 call_input_mux: in_mux_4_test
0784 PORT MAP(
0785 CLK40,
0786 ca11_reg, ca12_reg, ca13_reg, ca14_reg,
0787 ca21_reg, ca22_reg, ca23_reg, ca24_reg,
0788 ca31_reg, ca32_reg, ca33_reg, ca34_reg,
0789 ca41_reg, ca42_reg, ca43_reg, ca44_reg,
0790 ca51_reg, ca52_reg, ca53_reg, ca54_reg,
0791 ca61_reg, ca62_reg, ca63_reg, ca64_reg,
0792 ca71_reg, ca72_reg, ca73_reg, ca74_reg,
0793 ca81_reg, ca82_reg, ca83_reg, ca84_reg,
0794 ca91_reg, ca92_reg, ca93_reg, ca94_reg,
0795 ca101_reg, ca102_reg, ca103_reg, ca104_reg,
0796 mu1_reg, mu2_reg, mu3_reg, mu4_reg,
0797 algo_mux_in,
0798 ENCOND, WRCOND,
0799 ADDR, VDATA(15 DOWNTO 0),
0800 DTACK_MUX,
0801 algo_cond_mem);
0802
0803 -- ************* CONDITION (ALGO) MEMORY *******************************
0804 -- ALGO MEMORY AND TTC-SIGNALS INSTANTIATION
0805 -- HB010206: algo-memory 6 x 1024 x 16 bit !!!!
0806
0807 -- mif_file : STRING := "algo_1024_16.mif"
0808 -- mem_addr_cnt_width : integer := 10
0809 -- mem_data_width : integer := 16
0810 -- mem_width_base : integer := 3
0811 -- mem_width : integer := 6
0812 -- siehe cond_chip_pkg.vhd
0813
0814 call_cond_mem: cond_mem
0815 GENERIC MAP (algo_chip_name, mif_file, mem_addr_cnt_width,
0816 mem_data_width, mem_width_base, mem_width)
0817 PORT MAP(
0818 CLK_ALGO,
0819 algo_cond_mem,
0820 ENALGO, WRCOND,
0821 BCRES, L1A, L1RESET,
0822 ADDR, VDATA(15 DOWNTO 0),
0823 DTACK_COND_MEM,
0824 ALGO_OUT_REG_IN);
0825
0826 -- ************* ALGO OUT REGISTER *******************************
0827 -- output-register
0828 call_algo_out_reg: algo_out_reg
0829 GENERIC MAP(96, 3)
0830 PORT MAP(
0831 CLK_ALGO,
0832 ALGO_OUT_REG_IN, ALGOSTROB_reg,
0833 ALGO, ALGOSTROB);
0834
0835 -- ********************************************************************************************************
0836 -- condition-instantiations parts:
0837 -- RENAMING CALOs/MUONs
0838 -- MUON CHARGE INSTANTIATIONS
0839 -- CONDITION INSTANTIATIONS
0840 -- ********************************************************************************************************
0841
0842 -- ************* RENAMING CALOs/MUONs *******************************
0843 -- selecting and renaming of calorimeter- and muon-channels
0844 -- fix structure see CMS-IN_02_069.PDF (HB, 080104) !!!
0845 -- IEG inputs (channel 1)
0846 reg_ieg_et_1 <= ca11_reg(5 DOWNTO 0);
0847 reg_ieg_et_2 <= ca12_reg(5 DOWNTO 0);
0848 reg_ieg_et_3 <= ca13_reg(5 DOWNTO 0);
0849 reg_ieg_et_4 <= ca14_reg(5 DOWNTO 0);
0850 reg_ieg_eta_1 <= ca11_reg(9 DOWNTO 6);
0851 reg_ieg_eta_2 <= ca12_reg(9 DOWNTO 6);
0852 reg_ieg_eta_3 <= ca13_reg(9 DOWNTO 6);
0853 reg_ieg_eta_4 <= ca14_reg(9 DOWNTO 6);
0854 reg_ieg_phi_1 <= ca11_reg(14 DOWNTO 10);
0855 reg_ieg_phi_2 <= ca12_reg(14 DOWNTO 10);
0856 reg_ieg_phi_3 <= ca13_reg(14 DOWNTO 10);
0857 reg_ieg_phi_4 <= ca14_reg(14 DOWNTO 10);
0858 reg_ieg_sync_1 <= ca11_reg(15);
0859 reg_ieg_sync_2 <= ca12_reg(15);
0860 reg_ieg_sync_3 <= ca13_reg(15);
0861 reg_ieg_sync_4 <= ca14_reg(15);
0862 -- EG inputs (channel 2)
0863 reg_eg_et_1 <= ca21_reg(5 DOWNTO 0);
0864 reg_eg_et_2 <= ca22_reg(5 DOWNTO 0);
0865 reg_eg_et_3 <= ca23_reg(5 DOWNTO 0);
0866 reg_eg_et_4 <= ca24_reg(5 DOWNTO 0);
0867 reg_eg_eta_1 <= ca21_reg(9 DOWNTO 6);
0868 reg_eg_eta_2 <= ca22_reg(9 DOWNTO 6);
0869 reg_eg_eta_3 <= ca23_reg(9 DOWNTO 6);
0870 reg_eg_eta_4 <= ca24_reg(9 DOWNTO 6);
0871 reg_eg_phi_1 <= ca21_reg(14 DOWNTO 10);
0872 reg_eg_phi_2 <= ca22_reg(14 DOWNTO 10);
0873 reg_eg_phi_3 <= ca23_reg(14 DOWNTO 10);
0874 reg_eg_phi_4 <= ca24_reg(14 DOWNTO 10);
0875 reg_eg_sync_1 <= ca21_reg(15);
0876 reg_eg_sync_2 <= ca22_reg(15);
0877 reg_eg_sync_3 <= ca23_reg(15);
0878 reg_eg_sync_4 <= ca24_reg(15);
0879 -- cJET inputs (channel 3)
0880 reg_jet_et_1 <= ca31_reg(5 DOWNTO 0);
0881 reg_jet_et_2 <= ca32_reg(5 DOWNTO 0);
0882 reg_jet_et_3 <= ca33_reg(5 DOWNTO 0);
0883 reg_jet_et_4 <= ca34_reg(5 DOWNTO 0);
0884 reg_jet_eta_1 <= ca31_reg(9 DOWNTO 6);
0885 reg_jet_eta_2 <= ca32_reg(9 DOWNTO 6);
0886 reg_jet_eta_3 <= ca33_reg(9 DOWNTO 6);
0887 reg_jet_eta_4 <= ca34_reg(9 DOWNTO 6);
0888 reg_jet_phi_1 <= ca31_reg(14 DOWNTO 10);
0889 reg_jet_phi_2 <= ca32_reg(14 DOWNTO 10);
0890 reg_jet_phi_3 <= ca33_reg(14 DOWNTO 10);
0891 reg_jet_phi_4 <= ca34_reg(14 DOWNTO 10);
0892 reg_jet_sync_1 <= ca31_reg(15);
0893 reg_jet_sync_2 <= ca32_reg(15);
0894 reg_jet_sync_3 <= ca33_reg(15);
0895 reg_jet_sync_4 <= ca34_reg(15);
0896 -- fwdJET inputs (channel 4)
0897 reg_fwdjet_et_1 <= ca41_reg(5 DOWNTO 0);
0898 reg_fwdjet_et_2 <= ca42_reg(5 DOWNTO 0);
0899 reg_fwdjet_et_3 <= ca43_reg(5 DOWNTO 0);
0900 reg_fwdjet_et_4 <= ca44_reg(5 DOWNTO 0);
0901 reg_fwdjet_eta_1 <= ca41_reg(9 DOWNTO 6);
0902 reg_fwdjet_eta_2 <= ca42_reg(9 DOWNTO 6);
0903 reg_fwdjet_eta_3 <= ca43_reg(9 DOWNTO 6);
0904 reg_fwdjet_eta_4 <= ca44_reg(9 DOWNTO 6);
0905 reg_fwdjet_phi_1 <= ca41_reg(14 DOWNTO 10);
0906 reg_fwdjet_phi_2 <= ca42_reg(14 DOWNTO 10);
0907 reg_fwdjet_phi_3 <= ca43_reg(14 DOWNTO 10);
0908 reg_fwdjet_phi_4 <= ca44_reg(14 DOWNTO 10);
0909 reg_fwdjet_sync_1 <= ca41_reg(15);
0910 reg_fwdjet_sync_2 <= ca42_reg(15);
0911 reg_fwdjet_sync_3 <= ca43_reg(15);
0912 reg_fwdjet_sync_4 <= ca44_reg(15);
0913 -- TAU inputs (channel 5)
0914 reg_tau_et_1 <= ca51_reg(5 DOWNTO 0);
0915 reg_tau_et_2 <= ca52_reg(5 DOWNTO 0);
0916 reg_tau_et_3 <= ca53_reg(5 DOWNTO 0);
0917 reg_tau_et_4 <= ca54_reg(5 DOWNTO 0);
0918 reg_tau_eta_1 <= ca51_reg(9 DOWNTO 6);
0919 reg_tau_eta_2 <= ca52_reg(9 DOWNTO 6);
0920 reg_tau_eta_3 <= ca53_reg(9 DOWNTO 6);
0921 reg_tau_eta_4 <= ca54_reg(9 DOWNTO 6);
0922 reg_tau_phi_1 <= ca51_reg(14 DOWNTO 10);
0923 reg_tau_phi_2 <= ca52_reg(14 DOWNTO 10);
0924 reg_tau_phi_3 <= ca53_reg(14 DOWNTO 10);
0925 reg_tau_phi_4 <= ca54_reg(14 DOWNTO 10);
0926 reg_tau_sync_1 <= ca51_reg(15);
0927 reg_tau_sync_2 <= ca52_reg(15);
0928 reg_tau_sync_3 <= ca53_reg(15);
0929 reg_tau_sync_4 <= ca54_reg(15);
0930 -- energy summary information ("single objects") inputs (channel 6)
0931 reg_ett <= ca61_reg(12 DOWNTO 0);
0932 reg_esums_sync_1 <= ca61_reg(15);
0933 reg_etm <= ca62_reg(12 DOWNTO 0);
0934 reg_esums_sync_2 <= ca62_reg(15);
0935 reg_htt <= ca63_reg(12 DOWNTO 0);
0936 reg_esums_sync_3 <= ca63_reg(15);
0937 reg_etm_phi <= ca64_reg(6 DOWNTO 0);
0938 reg_esums_sync_4 <= ca64_reg(15);
0939 -- jet counts inputs (channel 7)
0940 reg_jet_cnts_0 <= ca71_reg(4 DOWNTO 0);
0941 reg_jet_cnts_1 <= ca71_reg(9 DOWNTO 5);
0942 reg_jet_cnts_2 <= ca71_reg(14 DOWNTO 10);
0943 reg_jet_cnts_sync_1 <= ca71_reg(15);
0944 reg_jet_cnts_3 <= ca72_reg(4 DOWNTO 0);
0945 reg_jet_cnts_4 <= ca72_reg(9 DOWNTO 5);
0946 reg_jet_cnts_5 <= ca72_reg(14 DOWNTO 10);
0947 reg_jet_cnts_sync_2 <= ca72_reg(15);
0948 reg_jet_cnts_6 <= ca73_reg(4 DOWNTO 0);
0949 reg_jet_cnts_7 <= ca73_reg(9 DOWNTO 5);
0950 reg_jet_cnts_8 <= ca73_reg(14 DOWNTO 10);
0951 reg_jet_cnts_sync_3 <= ca73_reg(15);
0952 reg_jet_cnts_9 <= ca74_reg(4 DOWNTO 0);
0953 reg_jet_cnts_10 <= ca74_reg(9 DOWNTO 5);
0954 reg_jet_cnts_11 <= ca74_reg(14 DOWNTO 10);
0955 reg_jet_cnts_sync_4 <= ca74_reg(15);
0956 -- MUON inputs
0957 reg_muon_pt_1 <= mu1_reg(12 DOWNTO 8);
0958 reg_muon_pt_2 <= mu2_reg(12 DOWNTO 8);
0959 reg_muon_pt_3 <= mu3_reg(12 DOWNTO 8);
0960 reg_muon_pt_4 <= mu4_reg(12 DOWNTO 8);
0961 reg_muon_eta_1 <= mu1_reg(21 DOWNTO 16);
0962 reg_muon_eta_2 <= mu2_reg(21 DOWNTO 16);
0963 reg_muon_eta_3 <= mu3_reg(21 DOWNTO 16);
0964 reg_muon_eta_4 <= mu4_reg(21 DOWNTO 16);
0965 reg_muon_phi_1 <= mu1_reg(7 DOWNTO 0);
0966 reg_muon_phi_2 <= mu2_reg(7 DOWNTO 0);
0967 reg_muon_phi_3 <= mu3_reg(7 DOWNTO 0);
0968 reg_muon_phi_4 <= mu4_reg(7 DOWNTO 0);
0969 reg_muon_qual_1 <= mu1_reg(15 DOWNTO 13);
0970 reg_muon_qual_2 <= mu2_reg(15 DOWNTO 13);
0971 reg_muon_qual_3 <= mu3_reg(15 DOWNTO 13);
0972 reg_muon_qual_4 <= mu4_reg(15 DOWNTO 13);
0973 reg_muon_iso_1 <= mu1_reg(22);
0974 reg_muon_iso_2 <= mu2_reg(22);
0975 reg_muon_iso_3 <= mu3_reg(22);
0976 reg_muon_iso_4 <= mu4_reg(22);
0977 reg_muon_mip_1 <= mu1_reg(23);
0978 reg_muon_mip_2 <= mu2_reg(23);
0979 reg_muon_mip_3 <= mu3_reg(23);
0980 reg_muon_mip_4 <= mu4_reg(23);
0981 reg_muon_sy_0_1 <= mu1_reg(24);
0982 reg_muon_sy_0_2 <= mu2_reg(24);
0983 reg_muon_sy_0_3 <= mu3_reg(24);
0984 reg_muon_sy_0_4 <= mu4_reg(24);
0985 reg_muon_sy_1_1 <= mu1_reg(25);
0986 reg_muon_sy_1_2 <= mu2_reg(25);
0987 reg_muon_sy_1_3 <= mu3_reg(25);
0988 reg_muon_sy_1_4 <= mu4_reg(25);
0989
0990 -- ************* MUON CHARGE INSTANTIATIONS *******************************
0991 -- muon charge instantiations, always instantiated
0992 -- compiler reduces unused logic
0993
0994 -- muon sync_word NOT used in VHDL Version 6.x
0995
0996 mu_ch_1: m_charge_cond_1
0997 PORT MAP (
0998 reg_muon_sy_0_1, reg_muon_sy_1_1,
0999 reg_muon_sy_0_2, reg_muon_sy_1_2,
1000 reg_muon_sy_0_3, reg_muon_sy_1_3,
1001 reg_muon_sy_0_4, reg_muon_sy_1_4,
1002 pos_lut_1, pos_lut_2, pos_lut_3, pos_lut_4,
1003 neg_lut_1, neg_lut_2, neg_lut_3, neg_lut_4);
1004
1005 mu_ch_2: m_charge_cond_2
1006 PORT MAP (
1007 reg_muon_sy_0_1, reg_muon_sy_1_1,
1008 reg_muon_sy_0_2, reg_muon_sy_1_2,
1009 reg_muon_sy_0_3, reg_muon_sy_1_3,
1010 reg_muon_sy_0_4, reg_muon_sy_1_4,
1011 eq_lut_12, eq_lut_13, eq_lut_14,
1012 eq_lut_23, eq_lut_24, eq_lut_34,
1013 neq_lut_12, neq_lut_13, neq_lut_14,
1014 neq_lut_23, neq_lut_24, neq_lut_34);
1015
1016 mu_ch_3: m_charge_cond_3
1017 PORT MAP (
1018 reg_muon_sy_0_1, reg_muon_sy_1_1,
1019 reg_muon_sy_0_2, reg_muon_sy_1_2,
1020 reg_muon_sy_0_3, reg_muon_sy_1_3,
1021 reg_muon_sy_0_4, reg_muon_sy_1_4,
1022 eq_lut_123, eq_lut_124, eq_lut_134, eq_lut_234,
1023 neq_lut_123, neq_lut_124, neq_lut_134, neq_lut_234);
1024
1025 mu_ch_4: m_charge_cond_4
1026 PORT MAP (
1027 reg_muon_sy_0_1, reg_muon_sy_1_1,
1028 reg_muon_sy_0_2, reg_muon_sy_1_2,
1029 reg_muon_sy_0_3, reg_muon_sy_1_3,
1030 reg_muon_sy_0_4, reg_muon_sy_1_4,
1031 eq_lut_1234, pair_lut);
1032
1033 -- ************* CONDITION INSTANTIATIONS *******************************
1034 -- variable part, depends on definitions in def.xml, generated by gts !!!
1035
1036 $(calo_common)
1037
1038 $(esums_common)
1039
1040 $(jet_cnts_common)
1041
1042 $(muon_common)
1043
1044 $(calo)
1045
1046 $(esums)
1047
1048 $(jet_cnts)
1049
1050 $(muon)
1051
1052 END ARCHITECTURE rtl;
