Warning, /L1TriggerConfig/L1GtConfigProducers/data/VhdlTemplates/Templates/pre_algo_and_or.vhd is written in an unsupported language. File is not indexed.
0001 $(header)
0002
0003 ------------------------------------------------------------
0004 -- --
0005 -- LOGIC CORE: GTL-9U-module condition/algo chip logic --
0006 -- MODULE NAME: algo_and_or --
0007 -- INSTITUTION: Hephy Vienna --
0008 -- DESIGNER: H. Bergauer --
0009 -- --
0010 -- VERSION: V4.0 --
0011 -- DATE: 06 2004 --
0012 -- --
0013 -- FUNCTIONAL DESCRIPTION: --
0014 -- algo logic (and-or) --
0015 -- --
0016 ------------------------------------------------------------
0017 LIBRARY ieee;
0018 USE ieee.std_logic_1164.ALL;
0019 ENTITY algo_and_or IS
0020 GENERIC (
0021 nr_ieg_4 : integer := 1;
0022 nr_ieg_2_s : integer := 1;
0023 nr_ieg_2_wsc : integer := 1;
0024 nr_ieg_1_s : integer := 1;
0025 nr_eg_4 : integer := 1;
0026 nr_eg_2_s : integer := 1;
0027 nr_eg_2_wsc : integer := 1;
0028 nr_eg_1_s : integer := 1;
0029 nr_jet_4 : integer := 1;
0030 nr_jet_2_s : integer := 1;
0031 nr_jet_2_wsc : integer := 1;
0032 nr_jet_1_s : integer := 1;
0033 nr_tau_4 : integer := 1;
0034 nr_tau_2_s : integer := 1;
0035 nr_tau_2_wsc : integer := 1;
0036 nr_tau_1_s : integer := 1;
0037 nr_fwdjet_4 : integer := 1;
0038 nr_fwdjet_2_s : integer := 1;
0039 nr_fwdjet_2_wsc : integer := 1;
0040 nr_fwdjet_1_s : integer := 1;
0041 nr_muon_4 : integer := 1;
0042 nr_muon_2_s : integer := 1;
0043 nr_muon_2_wsc : integer := 1;
0044 nr_muon_1_s : integer := 1;
0045 nr_muon_3 : integer := 1;
0046 nr_jet_cnts_0_cond : integer := 1;
0047 nr_jet_cnts_1_cond : integer := 1;
0048 nr_jet_cnts_2_cond : integer := 1;
0049 nr_jet_cnts_3_cond : integer := 1;
0050 nr_jet_cnts_4_cond : integer := 1;
0051 nr_jet_cnts_5_cond : integer := 1;
0052 nr_jet_cnts_6_cond : integer := 1;
0053 nr_jet_cnts_7_cond : integer := 1;
0054 nr_jet_cnts_8_cond : integer := 1;
0055 nr_jet_cnts_9_cond : integer := 1;
0056 nr_jet_cnts_10_cond : integer := 1;
0057 nr_jet_cnts_11_cond : integer := 1;
0058 nr_ett_cond : integer := 1;
0059 nr_etm_cond : integer := 1;
0060 nr_htt_cond : integer := 1);
0061 PORT(
0062 ieg_4 : IN STD_LOGIC_VECTOR(nr_ieg_4 DOWNTO 0);
0063 ieg_2_s : IN STD_LOGIC_VECTOR(nr_ieg_2_s DOWNTO 0);
0064 ieg_2_wsc : IN STD_LOGIC_VECTOR(nr_ieg_2_wsc DOWNTO 0);
0065 ieg_1_s : IN STD_LOGIC_VECTOR(nr_ieg_1_s DOWNTO 0);
0066 eg_4 : IN STD_LOGIC_VECTOR(nr_eg_4 DOWNTO 0);
0067 eg_2_s : IN STD_LOGIC_VECTOR(nr_eg_2_s DOWNTO 0);
0068 eg_2_wsc : IN STD_LOGIC_VECTOR(nr_eg_2_wsc DOWNTO 0);
0069 eg_1_s : IN STD_LOGIC_VECTOR(nr_eg_1_s DOWNTO 0);
0070 jet_4 : IN STD_LOGIC_VECTOR(nr_jet_4 DOWNTO 0);
0071 jet_2_s : IN STD_LOGIC_VECTOR(nr_jet_2_s DOWNTO 0);
0072 jet_2_wsc : IN STD_LOGIC_VECTOR(nr_jet_2_wsc DOWNTO 0);
0073 jet_1_s : IN STD_LOGIC_VECTOR(nr_jet_1_s DOWNTO 0);
0074 tau_4 : IN STD_LOGIC_VECTOR(nr_tau_4 DOWNTO 0);
0075 tau_2_s : IN STD_LOGIC_VECTOR(nr_tau_2_s DOWNTO 0);
0076 tau_2_wsc : IN STD_LOGIC_VECTOR(nr_tau_2_wsc DOWNTO 0);
0077 tau_1_s : IN STD_LOGIC_VECTOR(nr_tau_1_s DOWNTO 0);
0078 fwdjet_4 : IN STD_LOGIC_VECTOR(nr_fwdjet_4 DOWNTO 0);
0079 fwdjet_2_s : IN STD_LOGIC_VECTOR(nr_fwdjet_2_s DOWNTO 0);
0080 fwdjet_2_wsc: IN STD_LOGIC_VECTOR(nr_fwdjet_2_wsc DOWNTO 0);
0081 fwdjet_1_s : IN STD_LOGIC_VECTOR(nr_fwdjet_1_s DOWNTO 0);
0082 muon_4 : IN STD_LOGIC_VECTOR(nr_muon_4 DOWNTO 0);
0083 muon_2_s : IN STD_LOGIC_VECTOR(nr_muon_2_s DOWNTO 0);
0084 muon_2_wsc : IN STD_LOGIC_VECTOR(nr_muon_2_wsc DOWNTO 0);
0085 muon_1_s : IN STD_LOGIC_VECTOR(nr_muon_1_s DOWNTO 0);
0086 muon_3 : IN STD_LOGIC_VECTOR(nr_muon_3 DOWNTO 0);
0087 jet_cnts_0_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_0_cond DOWNTO 0);
0088 jet_cnts_1_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_1_cond DOWNTO 0);
0089 jet_cnts_2_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_2_cond DOWNTO 0);
0090 jet_cnts_3_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_3_cond DOWNTO 0);
0091 jet_cnts_4_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_4_cond DOWNTO 0);
0092 jet_cnts_5_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_5_cond DOWNTO 0);
0093 jet_cnts_6_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_6_cond DOWNTO 0);
0094 jet_cnts_7_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_7_cond DOWNTO 0);
0095 jet_cnts_8_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_8_cond DOWNTO 0);
0096 jet_cnts_9_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_9_cond DOWNTO 0);
0097 jet_cnts_10_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_10_cond DOWNTO 0);
0098 jet_cnts_11_cond: IN STD_LOGIC_VECTOR(nr_jet_cnts_11_cond DOWNTO 0);
0099 ett_cond: IN STD_LOGIC_VECTOR(nr_ett_cond DOWNTO 0);
0100 etm_cond: IN STD_LOGIC_VECTOR(nr_etm_cond DOWNTO 0);
0101 htt_cond: IN STD_LOGIC_VECTOR(nr_htt_cond DOWNTO 0);
0102 algo_s_reg : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
0103 algo_reg : INOUT STD_LOGIC_VECTOR(95 DOWNTO 0));
0104 END algo_and_or;
0105 ARCHITECTURE rtl OF algo_and_or IS
0106 SIGNAL pre_algo_a : STD_LOGIC_VECTOR(96 DOWNTO 1);
0107 BEGIN
0108
0109 -- "NO ALGO"-bit
0110 ALGO_S_REG(0) <= NOT(
0111 ALGO_REG(0) OR ALGO_REG(1) OR ALGO_REG(2) OR ALGO_REG(3)
0112 OR
0113 ALGO_REG(4) OR ALGO_REG(5) OR ALGO_REG(6) OR ALGO_REG(7)
0114 OR
0115 ALGO_REG(8) OR ALGO_REG(9) OR ALGO_REG(10) OR ALGO_REG(11)
0116 OR
0117 ALGO_REG(12) OR ALGO_REG(13) OR ALGO_REG(14) OR ALGO_REG(15)
0118 OR
0119 ALGO_REG(16) OR ALGO_REG(17) OR ALGO_REG(18) OR ALGO_REG(19)
0120 OR
0121 ALGO_REG(20) OR ALGO_REG(21) OR ALGO_REG(22) OR ALGO_REG(23)
0122 OR
0123 ALGO_REG(24) OR ALGO_REG(25) OR ALGO_REG(26) OR ALGO_REG(27)
0124 OR
0125 ALGO_REG(28) OR ALGO_REG(29) OR ALGO_REG(30) OR ALGO_REG(31));
0126
0127 ALGO_S_REG(1) <= NOT(
0128 ALGO_REG(32) OR ALGO_REG(33) OR ALGO_REG(34) OR ALGO_REG(53)
0129 OR
0130 ALGO_REG(36) OR ALGO_REG(37) OR ALGO_REG(38) OR ALGO_REG(39)
0131 OR
0132 ALGO_REG(40) OR ALGO_REG(41) OR ALGO_REG(42) OR ALGO_REG(43)
0133 OR
0134 ALGO_REG(44) OR ALGO_REG(45) OR ALGO_REG(46) OR ALGO_REG(47)
0135 OR
0136 ALGO_REG(48) OR ALGO_REG(49) OR ALGO_REG(50) OR ALGO_REG(51)
0137 OR
0138 ALGO_REG(52) OR ALGO_REG(53) OR ALGO_REG(54) OR ALGO_REG(55)
0139 OR
0140 ALGO_REG(56) OR ALGO_REG(57) OR ALGO_REG(58) OR ALGO_REG(59)
0141 OR
0142 ALGO_REG(60) OR ALGO_REG(61) OR ALGO_REG(62) OR ALGO_REG(63));
0143
0144 ALGO_S_REG(2) <= NOT(
0145 ALGO_REG(64) OR ALGO_REG(65) OR ALGO_REG(66) OR ALGO_REG(67)
0146 OR
0147 ALGO_REG(68) OR ALGO_REG(69) OR ALGO_REG(70) OR ALGO_REG(71)
0148 OR
0149 ALGO_REG(72) OR ALGO_REG(73) OR ALGO_REG(74) OR ALGO_REG(75)
0150 OR
0151 ALGO_REG(76) OR ALGO_REG(77) OR ALGO_REG(78) OR ALGO_REG(79)
0152 OR
0153 ALGO_REG(80) OR ALGO_REG(81) OR ALGO_REG(82) OR ALGO_REG(83)
0154 OR
0155 ALGO_REG(84) OR ALGO_REG(85) OR ALGO_REG(86) OR ALGO_REG(87)
0156 OR
0157 ALGO_REG(88) OR ALGO_REG(89) OR ALGO_REG(90) OR ALGO_REG(91)
0158 OR
0159 ALGO_REG(92) OR ALGO_REG(93) OR ALGO_REG(94) OR ALGO_REG(95));
0160
0161 -- ***************************************************************
0162
0163 ALGO_REG(95 DOWNTO 0) <= pre_algo_a(96 DOWNTO 1);
0164
0165 $(prealgos)
0166
0167 END ARCHITECTURE rtl;
