SiPixelObjects/src/PixelFEDCard.cc

0001 // Read the pixelFED setup parameters from an ASCII file
0002 // Will Johns & Danek Kotlinski 04/06.
0003
0004 #include <iostream>
0005
0006 #include "CalibFormats/SiPixelObjects/interface/PixelFEDCard.h"
0007 #include "CalibFormats/SiPixelObjects/interface/PixelTimeFormatter.h"
0008
0009 #include <cassert>
0010 #include <sstream>
0011 #include <map>
0012 #include <stdexcept>
0013
0014 using namespace std;
0015
0016 using namespace pos;
0017
0018 PixelFEDCard::PixelFEDCard() : PixelConfigBase(" ", " ", " ") { clear(); }
0019
0020 // modified by MR on 24-04-2008 12:05:42
0021 // Read configuration from DB
0022 PixelFEDCard::PixelFEDCard(vector<vector<string> > &tableMat) : PixelConfigBase(" ", " ", " ") {
0023   std::string mthn = "[PixelFEDCard::PixelFEDCard()]\t\t    ";
0024   vector<string> ins = tableMat[0];
0025   map<string, int> colM;
0026   vector<string> colNames;
0027   /**
0028     EXTENSION_TABLE_NAME: FED_CONFIGURATION (VIEW: CONF_KEY_FED_CONFIGURATION_V)
0029
0030     Name                       Null?    Type           POS variable
0031     ------------------------ -------- ---------------------------------------------------------------
0032
0033     BUSYWHENBEHIND                 NUMBER(38)
0034     FEATUREREGISTER                VARCHAR2(200)
0035     FIFO2LIMIT                     VARCHAR2(200)
0036     TIMEOUTOROOSLIMIT              NUMBER(38)
0037     LASTDACOFF                     NUMBER(38)
0038     SIMHITSPERROC                  NUMBER(38)
0039     BUSYHOLDMIN                    NUMBER(38)
0040     SPARE1                     NUMBER(38)
0041     SPARE2                     NUMBER(38)
0042     SPARE3                     NUMBER(38)
0043     SPARE4                     NUMBER(38)
0044     SPARE5                     NUMBER(38)
0045     SPARE6                     NUMBER(38)
0046     SPARE7                     NUMBER(38)
0047     SPARE8                     NUMBER(38)
0048     SPARE9                     NUMBER(38)
0049     SPARE10                            NUMBER(38)
0050     CONFIG_KEY            NOT NULL VARCHAR2(80)
0051     KEY_TYPE              NOT NULL VARCHAR2(80)
0052     KEY_ALIAS_ID
0053     KEY_ALIAS             NOT NULL VARCHAR2(80)
0054     VERSION                    VARCHAR2(40)
0055     KIND_OF_COND          NOT NULL VARCHAR2(40)
0056     CRATE_LABEL                    VARCHAR2(200)
0057     CRATE_NUMBER                   NUMBER(38)
0058     SLOT_NUMBER                    NUMBER(38)
0059     VME_ADDRS_HEX         NOT NULL VARCHAR2(200)         FEDBASE_0
0060     PIXEL_FED             NOT NULL NUMBER(38)        fedNumber
0061     CHANNEL_ID            NOT NULL NUMBER(38)
0062     NUM_ROCS              NOT NULL NUMBER(38)        NRocs[1-36]    index taken from CHANNEL_ID
0063     CHAN_OFFST_DAC        NOT NULL NUMBER(38)        offs_dac[1-36] index taken from CHANNEL_ID
0064     CHAN_DELAY            NOT NULL NUMBER(38)        DelayCh[1-36]  index taken from CHANNEL_ID
0065     CHAN_BHIGH            NOT NULL NUMBER(38)        BlackHi[1-36]  index taken from CHANNEL_ID
0066     CHAN_BLOW             NOT NULL NUMBER(38)        BlackLo[1-36]  index taken from CHANNEL_ID
0067     CHAN_UB           NOT NULL NUMBER(38)        Ublack[1-36]   index taken from CHANNEL_ID
0068     OPT1_CAP              NOT NULL NUMBER(38)        opt_cap[0]
0069     OPT2_CAP              NOT NULL NUMBER(38)        opt_cap[1]
0070     OPT3_CAP              NOT NULL NUMBER(38)        opt_cap[2]
0071     OPT1_INP              NOT NULL NUMBER(38)        opt_inadj[0]
0072     OPT2_INP              NOT NULL NUMBER(38)        opt_inadj[1]
0073     OPT3_INP              NOT NULL NUMBER(38)        opt_inadj[2]
0074     OPT1_OUT              NOT NULL NUMBER(38)        opt_ouadj[0]
0075     OPT2_OUT              NOT NULL NUMBER(38)        opt_ouadj[1]
0076     OPT3_OUT              NOT NULL NUMBER(38)        opt_ouadj[2]
0077     NORTH_CLKPHB          NOT NULL NUMBER(38)        clkphs1_9
0078     NORTHCENTER_CLKPHB        NOT NULL NUMBER(38)        clkphs10_18
0079     SOUTHCENTER_CLKPHB        NOT NULL NUMBER(38)        clkphs19_27
0080     SOUTH_CLKPHB          NOT NULL NUMBER(38)        clkphs28_36
0081     NORTH_CTRL            NOT NULL NUMBER(38)        Ncntrl
0082     NORTHCENTER_CTRL          NOT NULL NUMBER(38)        NCcntrl
0083     SOUTHCENTER_CTRL          NOT NULL NUMBER(38)        SCcntrl
0084     SOUTH_CTRL            NOT NULL NUMBER(38)        Scntrl
0085     REG0_TTCRX_FDLA                                      FineDes1Del
0086     REG1_TTCRX_FDLA       NOT NULL NUMBER(38)        FineDes2Del
0087     REG2_TTCRX_CDLA       NOT NULL NUMBER(38)        CoarseDel
0088     REG3_TTCRX_CLKD2          NOT NULL NUMBER(38)        ClkDes2
0089     CENTER_CTRL           NOT NULL NUMBER(38)        Ccntrl
0090     CENTER_MODE           NOT NULL NUMBER(38)        modeRegister
0091     B1_ADCGN              NOT NULL NUMBER(38)        Nadcg
0092     B2_ADCGN              NOT NULL NUMBER(38)        NCadcg
0093     B3_ADCGN              NOT NULL NUMBER(38)        SCadcg
0094     B4_ADCGN              NOT NULL NUMBER(38)        Sadcg
0095     NORTH_BADJ            NOT NULL NUMBER(38)        Nbaseln
0096     NORTHCENTER_BADJ          NOT NULL NUMBER(38)        NCbaseln
0097     SOUTHCENTER_BADJ          NOT NULL NUMBER(38)        SCbaseln
0098     SOUTH_BADJ            NOT NULL NUMBER(38)        Sbaseln
0099     NORTH_TBMMASK         NOT NULL NUMBER(38)        N_TBMmask
0100     NORTHCENTER_TBMMASK       NOT NULL NUMBER(38)        NC_TBMmask
0101     SOUTHCENTER_TBMMASK       NOT NULL NUMBER(38)        SC_TBMmask
0102     SOUTH_TBMMASK         NOT NULL NUMBER(38)        S_TBMmask
0103     NORTH_PWORD           NOT NULL NUMBER(38)        N_Pword
0104     NORTHCENTER_PWORD         NOT NULL NUMBER(38)        NC_Pword
0105     SOUTH_PWORD           NOT NULL NUMBER(38)        S_Pword
0106     SOUTHCENTER_PWORD         NOT NULL NUMBER(38)        SC_Pword
0107     SPECDAC           NOT NULL NUMBER(38)        SpecialDac
0108     OOS_LVL           NOT NULL NUMBER(38)        Ooslvl
0109     ERR_LVL           NOT NULL NUMBER(38)        Errlvl
0110     NORTH_FIFO1_BZ_LVL        NOT NULL NUMBER(38)        Nfifo1Bzlvl
0111     NORTHCENTER_FIFO1_BZ_LVL  NOT NULL NUMBER(38)        NCfifo1Bzlvl
0112     SOUTHCENTER_FIFO1_BZ_LVL  NOT NULL NUMBER(38)        SCfifo1Bzlvl
0113     SOUTH_FIFO1_BZ_LVL        NOT NULL NUMBER(38)        Sfifo1Bzlvl
0114     FIFO3_WRN_LVL              NUMBER(38)        fifo3Wrnlvl
0115     FED_MASTER_DELAY               NUMBER(38)        FedTTCDelay
0116     NO_HITLIMIT                NUMBER(38)        N_hitlimit
0117     NC_HITLIMIT                NUMBER(38)        NC_hitlimit
0118     SC_HITLIMIT                NUMBER(38)        SC_hitlimit
0119     SO_HITLIMIT                NUMBER(38)        S_hitlimit
0120     NO_TESTREG                 NUMBER(38)        N_testreg
0121     NC_TESTREG                 NUMBER(38)        NC_testreg
0122     SC_TESTREG                 NUMBER(38)        SC_testreg
0123     SO_TESTREG                 NUMBER(38)        S_testreg
0124     TRIGGERHOLDOFF
0125
0126 */
0127   colNames.push_back("BUSYWHENBEHIND");
0128   colNames.push_back("FEATUREREGISTER");
0129   colNames.push_back("FIFO2LIMIT");
0130   colNames.push_back("TIMEOUTOROOSLIMIT");
0131   colNames.push_back("LASTDACOFF");
0132   colNames.push_back("SIMHITSPERROC");
0133   colNames.push_back("BUSYHOLDMIN");
0134   colNames.push_back("SPARE1");
0135   colNames.push_back("SPARE2");
0136   colNames.push_back("SPARE3");
0137   colNames.push_back("SPARE4");
0138   colNames.push_back("SPARE5");
0139   colNames.push_back("SPARE6");
0140   colNames.push_back("SPARE7");
0141   colNames.push_back("SPARE8");
0142   colNames.push_back("SPARE9");
0143   colNames.push_back("SPARE10");
0144   colNames.push_back("CONFIG_KEY");
0145   colNames.push_back("KEY_TYPE");
0146   colNames.push_back("KEY_ALIAS_ID");
0147   colNames.push_back("KEY_ALIAS");
0148   colNames.push_back("VERSION");
0149   colNames.push_back("KIND_OF_COND");
0150   colNames.push_back("CRATE_LABEL");
0151   colNames.push_back("CRATE_NUMBER");
0152   colNames.push_back("SLOT_NUMBER");
0153   colNames.push_back("VME_ADDRS_HEX");
0154   colNames.push_back("PIXEL_FED");
0155   colNames.push_back("CHANNEL_ID");
0156   colNames.push_back("NUM_ROCS");
0157   colNames.push_back("CHAN_OFFST_DAC");
0158   colNames.push_back("CHAN_DELAY");
0159   colNames.push_back("CHAN_BHIGH");
0160   colNames.push_back("CHAN_BLOW");
0161   colNames.push_back("CHAN_UB");
0162   colNames.push_back("OPT1_CAP");
0163   colNames.push_back("OPT2_CAP");
0164   colNames.push_back("OPT3_CAP");
0165   colNames.push_back("OPT1_INP");
0166   colNames.push_back("OPT2_INP");
0167   colNames.push_back("OPT3_INP");
0168   colNames.push_back("OPT1_OUT");
0169   colNames.push_back("OPT2_OUT");
0170   colNames.push_back("OPT3_OUT");
0171   colNames.push_back("NORTH_CLKPHB");
0172   colNames.push_back("NORTHCENTER_CLKPHB");
0173   colNames.push_back("SOUTHCENTER_CLKPHB");
0174   colNames.push_back("SOUTH_CLKPHB");
0175   colNames.push_back("NORTH_CTRL");
0176   colNames.push_back("NORTHCENTER_CTRL");
0177   colNames.push_back("SOUTHCENTER_CTRL");
0178   colNames.push_back("SOUTH_CTRL");
0179   colNames.push_back("REG0_TTCRX_FDLA");
0180   colNames.push_back("REG1_TTCRX_FDLA");
0181   colNames.push_back("REG2_TTCRX_CDLA");
0182   colNames.push_back("REG3_TTCRX_CLKD2");
0183   colNames.push_back("CENTER_CTRL");
0184   colNames.push_back("CENTER_MODE");
0185   colNames.push_back("B1_ADCGN");
0186   colNames.push_back("B2_ADCGN");
0187   colNames.push_back("B3_ADCGN");
0188   colNames.push_back("B4_ADCGN");
0189   colNames.push_back("NORTH_BADJ");
0190   colNames.push_back("NORTHCENTER_BADJ");
0191   colNames.push_back("SOUTHCENTER_BADJ");
0192   colNames.push_back("SOUTH_BADJ");
0193   colNames.push_back("NORTH_TBMMASK");
0194   colNames.push_back("NORTHCENTER_TBMMASK");
0195   colNames.push_back("SOUTHCENTER_TBMMASK");
0196   colNames.push_back("SOUTH_TBMMASK");
0197   colNames.push_back("NORTH_PWORD");
0198   colNames.push_back("NORTHCENTER_PWORD");
0199   colNames.push_back("SOUTH_PWORD");
0200   colNames.push_back("SOUTHCENTER_PWORD");
0201   colNames.push_back("SPECDAC");
0202   colNames.push_back("OOS_LVL");
0203   colNames.push_back("ERR_LVL");
0204   colNames.push_back("NORTH_FIFO1_BZ_LVL");
0205   colNames.push_back("NORTHCENTER_FIFO1_BZ_LVL");
0206   colNames.push_back("SOUTHCENTER_FIFO1_BZ_LVL");
0207   colNames.push_back("SOUTH_FIFO1_BZ_LVL");
0208   colNames.push_back("FIFO3_WRN_LVL");
0209   colNames.push_back("FED_MASTER_DELAY");
0210   colNames.push_back("NO_HITLIMIT");
0211   colNames.push_back("NC_HITLIMIT");
0212   colNames.push_back("SC_HITLIMIT");
0213   colNames.push_back("SO_HITLIMIT");
0214   colNames.push_back("NO_TESTREG");
0215   colNames.push_back("NC_TESTREG");
0216   colNames.push_back("SC_TESTREG");
0217   colNames.push_back("SO_TESTREG");
0218   colNames.push_back("TRIGGERHOLDOFF");
0219
0220   for (unsigned int c = 0; c < ins.size(); c++) {
0221     for (unsigned int n = 0; n < colNames.size(); n++) {
0222       if (tableMat[0][c] == colNames[n]) {
0223         colM[colNames[n]] = c;
0224         break;
0225       }
0226     }
0227   }  //end for
0228   for (unsigned int n = 0; n < colNames.size(); n++) {
0229     if (colM.find(colNames[n]) == colM.end()) {
0230       std::cerr << __LINE__ << "]\t[PixelFEDCard::PixelFEDCard]\tCouldn't find in the database the column with name "
0231                 << colNames[n] << std::endl;
0232       assert(0);
0233     }
0234   }
0235   // disentagle different tables
0236   int size[3];
0237   int indexsize = 0;
0238   for (unsigned int r = 0; r < tableMat.size(); r++) {  //Goes to every row of the Matrix
0239     if (tableMat[r].empty()) {
0240       //        cout << __LINE__ << "]\t" << mthn << "__________________ NEW TABLE __________________"<< endl ;
0241       size[indexsize] = r;
0242       //        cout << __LINE__ << "]\t" << mthn << "size[" << indexsize << "] = " << size[indexsize] << endl ;
0243       indexsize++;
0244       continue;
0245     }
0246     for (vector<string>::iterator it = tableMat[r].begin(); it != tableMat[r].end(); ++it) {
0247       //      cout << __LINE__ << "]\t" << mthn << *it <<"["<<&*it<<"]\t"  ;
0248       //      cout << __LINE__ << "]\t" << mthn << *it <<"\t"  ;
0249     }
0250     //    cout << __LINE__ << "]\t" << mthn << endl ;
0251   }
0252
0253   // Read below quantities pertaining to a single FED that are equal accross 36 channels
0254
0255   //VME base address
0256   //Fed Base Address
0257   sscanf(tableMat[1][colM["VME_ADDRS_HEX"]].c_str(), "%lx", &FEDBASE_0);
0258   //      sscanf(tableMat[1][colM["PIXEL_FED"]].c_str(), "PxlFED_%ld",&fedNumber);
0259   fedNumber = atoi(tableMat[1][colM["PIXEL_FED"]].c_str());
0260   //Settable optical input parameters (one for each 12-receiver)
0261   opt_cap[0] = atoi(tableMat[1][colM["OPT1_CAP"]].c_str());
0262   opt_cap[1] = atoi(tableMat[1][colM["OPT2_CAP"]].c_str());
0263   opt_cap[2] = atoi(tableMat[1][colM["OPT3_CAP"]].c_str());
0264   opt_inadj[0] = atoi(tableMat[1][colM["OPT1_INP"]].c_str());
0265   opt_inadj[1] = atoi(tableMat[1][colM["OPT2_INP"]].c_str());
0266   opt_inadj[2] = atoi(tableMat[1][colM["OPT3_INP"]].c_str());
0267   opt_ouadj[0] = atoi(tableMat[1][colM["OPT1_OUT"]].c_str());
0268   opt_ouadj[1] = atoi(tableMat[1][colM["OPT2_OUT"]].c_str());
0269   opt_ouadj[2] = atoi(tableMat[1][colM["OPT3_OUT"]].c_str());
0270
0271   //clock phases, use bits 0-8, select the clock edged
0272   clkphs1_9 = atoi(tableMat[1][colM["NORTH_CLKPHB"]].c_str());          // TO BE VERIFIED
0273   clkphs10_18 = atoi(tableMat[1][colM["NORTHCENTER_CLKPHB"]].c_str());  // TO BE VERIFIED
0274   clkphs19_27 = atoi(tableMat[1][colM["SOUTHCENTER_CLKPHB"]].c_str());  // TO BE VERIFIED
0275   clkphs28_36 = atoi(tableMat[1][colM["SOUTH_CLKPHB"]].c_str());        // TO BE VERIFIED
0276
0277   // Control register and delays for the TTCrx
0278   FineDes1Del = atoi(tableMat[1][colM["REG0_TTCRX_FDLA"]].c_str());
0279   FineDes2Del = atoi(tableMat[1][colM["REG1_TTCRX_FDLA"]].c_str());
0280   CoarseDel = atoi(tableMat[1][colM["REG2_TTCRX_CDLA"]].c_str());
0281   ClkDes2 = atoi(tableMat[1][colM["REG3_TTCRX_CLKD2"]].c_str());
0282
0283   Ccntrl = atoi(tableMat[1][colM["CENTER_CTRL"]].c_str());
0284   modeRegister = atoi(tableMat[1][colM["CENTER_MODE"]].c_str());
0285
0286   //data Regs adjustable fifo Almost Full levels
0287   Nfifo1Bzlvl = atoi(tableMat[1][colM["NORTH_FIFO1_BZ_LVL"]].c_str());
0288   NCfifo1Bzlvl = atoi(tableMat[1][colM["NORTHCENTER_FIFO1_BZ_LVL"]].c_str());
0289   SCfifo1Bzlvl = atoi(tableMat[1][colM["SOUTHCENTER_FIFO1_BZ_LVL"]].c_str());
0290   Sfifo1Bzlvl = atoi(tableMat[1][colM["SOUTH_FIFO1_BZ_LVL"]].c_str());
0291
0292   //Bits (1st 8) used to mask TBM trailer bits
0293   N_TBMmask = atoi(tableMat[1][colM["NORTH_TBMMASK"]].c_str());
0294   NC_TBMmask = atoi(tableMat[1][colM["NORTHCENTER_TBMMASK"]].c_str());
0295   SC_TBMmask = atoi(tableMat[1][colM["SOUTHCENTER_TBMMASK"]].c_str());
0296   S_TBMmask = atoi(tableMat[1][colM["SOUTH_TBMMASK"]].c_str());
0297
0298   //Bits (1st 8) used to set the Private Word in the gap and filler words
0299   N_Pword = atoi(tableMat[1][colM["NORTH_PWORD"]].c_str());
0300   NC_Pword = atoi(tableMat[1][colM["NORTHCENTER_PWORD"]].c_str());
0301   SC_Pword = atoi(tableMat[1][colM["SOUTHCENTER_PWORD"]].c_str());
0302   S_Pword = atoi(tableMat[1][colM["SOUTH_PWORD"]].c_str());
0303
0304   Nbaseln = atoi(tableMat[1][colM["NORTH_BADJ"]].c_str());
0305   NCbaseln = atoi(tableMat[1][colM["NORTHCENTER_BADJ"]].c_str());
0306   SCbaseln = atoi(tableMat[1][colM["SOUTHCENTER_BADJ"]].c_str());
0307   Sbaseln = atoi(tableMat[1][colM["SOUTH_BADJ"]].c_str());
0308
0309   Ncntrl = atoi(tableMat[1][colM["NORTH_CTRL"]].c_str());
0310   NCcntrl = atoi(tableMat[1][colM["NORTHCENTER_CTRL"]].c_str());
0311   SCcntrl = atoi(tableMat[1][colM["SOUTHCENTER_CTRL"]].c_str());
0312   Scntrl = atoi(tableMat[1][colM["SOUTH_CTRL"]].c_str());
0313
0314   //These bit sets the special dac mode for random triggers
0315   SpecialDac = atoi(tableMat[1][colM["SPECDAC"]].c_str());
0316
0317   //These bits set the number of Out of consecutive out of sync events until a TTs OOs
0318   Ooslvl = atoi(tableMat[1][colM["OOS_LVL"]].c_str());
0319   //These bits set the number of Empty events until a TTs Error
0320   Errlvl = atoi(tableMat[1][colM["ERR_LVL"]].c_str());
0321
0322   //Control Regs for setting ADC 1Vpp and 2Vpp
0323   Nadcg = atoi(tableMat[1][colM["B1_ADCGN"]].c_str());
0324   NCadcg = atoi(tableMat[1][colM["B2_ADCGN"]].c_str());
0325   SCadcg = atoi(tableMat[1][colM["B3_ADCGN"]].c_str());
0326   Sadcg = atoi(tableMat[1][colM["B4_ADCGN"]].c_str());
0327   fifo3Wrnlvl = atoi(tableMat[1][colM["FIFO3_WRN_LVL"]].c_str());
0328   FedTTCDelay = atoi(tableMat[1][colM["FED_MASTER_DELAY"]].c_str());
0329   N_hitlimit = atoi(tableMat[1][colM["NO_HITLIMIT"]].c_str());
0330   NC_hitlimit = atoi(tableMat[1][colM["NC_HITLIMIT"]].c_str());
0331   SC_hitlimit = atoi(tableMat[1][colM["SC_HITLIMIT"]].c_str());
0332   S_hitlimit = atoi(tableMat[1][colM["SO_HITLIMIT"]].c_str());
0333   N_testreg = atoi(tableMat[1][colM["NO_TESTREG"]].c_str());
0334   NC_testreg = atoi(tableMat[1][colM["NC_TESTREG"]].c_str());
0335   SC_testreg = atoi(tableMat[1][colM["SC_TESTREG"]].c_str());
0336   S_testreg = atoi(tableMat[1][colM["SO_TESTREG"]].c_str());
0337   BusyHoldMin = atoi(tableMat[1][colM["BUSYHOLDMIN"]].c_str());
0338   BusyWhenBehind = atoi(tableMat[1][colM["BUSYWHENBEHIND"]].c_str());
0339   FeatureRegister = atoi(tableMat[1][colM["FEATUREREGISTER"]].c_str());
0340   FIFO2Limit = atoi(tableMat[1][colM["FIFO2LIMIT"]].c_str());
0341   LastDacOff = atoi(tableMat[1][colM["LASTDACOFF"]].c_str());
0342   SimHitsPerRoc = atoi(tableMat[1][colM["SIMHITSPERROC"]].c_str());
0343   TimeoutOROOSLimit = atoi(tableMat[1][colM["TIMEOUTOROOSLIMIT"]].c_str());
0344   TriggerHoldoff = atoi(tableMat[1][colM["TRIGGERHOLDOFF"]].c_str());
0345
0346   SPARE1 = atoi(tableMat[1][colM["SPARE1"]].c_str());
0347   SPARE2 = atoi(tableMat[1][colM["SPARE2"]].c_str());
0348   SPARE3 = atoi(tableMat[1][colM["SPARE3"]].c_str());
0349   SPARE4 = atoi(tableMat[1][colM["SPARE4"]].c_str());
0350   SPARE5 = atoi(tableMat[1][colM["SPARE5"]].c_str());
0351   SPARE6 = atoi(tableMat[1][colM["SPARE6"]].c_str());
0352   SPARE7 = atoi(tableMat[1][colM["SPARE7"]].c_str());
0353   SPARE8 = atoi(tableMat[1][colM["SPARE8"]].c_str());
0354   SPARE9 = atoi(tableMat[1][colM["SPARE9"]].c_str());
0355   SPARE10 = atoi(tableMat[1][colM["SPARE10"]].c_str());
0356
0357   [[clang::suppress]]
0358   for (int r = 1; r < size[0]; r++)  //Goes to every row of the FIRST Matrix (MUST BE 36, one for each FED channel)
0359   {
0360     //Number of ROCS per FED channel
0361     NRocs[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["NUM_ROCS"]].c_str());
0362     //input offset dac (one for each channel)
0363     offs_dac[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_OFFST_DAC"]].c_str());
0364     //Channel delays, one for each channel, 0=15
0365     DelayCh[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_DELAY"]].c_str());
0366     //Blacks and Ultra-blacks, 3 limit per channel
0367     BlackHi[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_BHIGH"]].c_str());
0368     BlackLo[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_BLOW"]].c_str());
0369     Ublack[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_UB"]].c_str());
0370   }
0371
0372   [[clang::suppress]] readDBTBMLevels(tableMat, size[0] + 1, size[1]);
0373   [[clang::suppress]] readDBROCLevels(tableMat, size[1] + 1, size[2]);
0374   Ccntrl_original = Ccntrl;
0375   modeRegister_original = modeRegister;
0376
0377   Ncntrl_original = Ncntrl;
0378   NCcntrl_original = NCcntrl;
0379   SCcntrl_original = SCcntrl;
0380   Scntrl_original = Scntrl;
0381
0382   Nbaseln_original = Nbaseln;
0383   NCbaseln_original = NCbaseln;
0384   SCbaseln_original = SCbaseln;
0385   Sbaseln_original = Sbaseln;
0386
0387   // Modified by MR on 17-11-2008
0388   // This new variable has to be read from DB!!!!!
0389   // We need to add a column in the DB. Talk to Umesh.
0390   FineDes1Del = 14;
0391 }
0392
0393 void PixelFEDCard::readDBTBMLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow) {
0394   string mthn = "[PixelFEDCard::readDBTBMLevels()] ";
0395   vector<string> ins = tableMat[firstRow];
0396   map<string, int> colM;
0397   vector<string> colNames;
0398
0399   /**
0400      EXTERNAL_TABLE_NAME: TBM_ANALOG_LEVELS (VIEW: CONF_KEY_TBM_LEVELS_V)
0401
0402      CONFIG_KEY                    NOT NULL VARCHAR2(80)
0403      KEY_TYPE                      NOT NULL VARCHAR2(80)
0404      KEY_ALIAS                     NOT NULL VARCHAR2(80)
0405      VERSION                        VARCHAR2(40)
0406      KIND_OF_COND                  NOT NULL VARCHAR2(40)
0407      TBM_NAME                                           VARCHAR2(200)
0408      PIXEL_FED                                          NUMBER(38)
0409      FED_CHAN                                           NUMBER(38)
0410      TBMA_HEAD_L0                                       NUMBER(38)    TBM_L0[1-36] index taken from FED_CHAN
0411      TBMA_HEAD_L1                                       NUMBER(38)    TBM_L1[1-36] index taken from FED_CHAN
0412      TBMA_HEAD_L2                                       NUMBER(38)    TBM_L2[1-36] index taken from FED_CHAN
0413      TBMA_HEAD_L3                                       NUMBER(38)    TBM_L3[1-36] index taken from FED_CHAN
0414      TBMA_HEAD_L4                                       NUMBER(38)    TBM_L4[1-36] index taken from FED_CHAN
0415      TBMA_TRAIL_L0                                      NUMBER(38)    TRL_L0[1-36] index taken from FED_CHAN
0416      TBMA_TRAIL_L1                                      NUMBER(38)    TRL_L1[1-36] index taken from FED_CHAN
0417      TBMA_TRAIL_L2                                      NUMBER(38)    TRL_L2[1-36] index taken from FED_CHAN
0418      TBMA_TRAIL_L3                                      NUMBER(38)    TRL_L3[1-36] index taken from FED_CHAN
0419      TBMA_TRAIL_L4                                      NUMBER(38)    TRL_L4[1-36] index taken from FED_CHAN
0420      TBMA_HEAD_B                                        NUMBER(38)
0421      TBMA_HEAD_UB                                       NUMBER(38)
0422      TBMA_TRAIL_B                                       NUMBER(38)
0423      TBMA_TRAIL_UB                                      NUMBER(38)
0424
0425   */
0426
0427   colNames.push_back("CONFIG_KEY");
0428   colNames.push_back("KEY_TYPE");
0429   colNames.push_back("KEY_ALIAS");
0430   colNames.push_back("VERSION");
0431   colNames.push_back("KIND_OF_COND");
0432   colNames.push_back("TBM_NAME");
0433   colNames.push_back("PIXEL_FED");
0434   colNames.push_back("FED_CHAN");
0435   colNames.push_back("TBMA_HEAD_L0");
0436   colNames.push_back("TBMA_HEAD_L1");
0437   colNames.push_back("TBMA_HEAD_L2");
0438   colNames.push_back("TBMA_HEAD_L3");
0439   colNames.push_back("TBMA_HEAD_L4");
0440   colNames.push_back("TBMA_TRAIL_L0");
0441   colNames.push_back("TBMA_TRAIL_L1");
0442   colNames.push_back("TBMA_TRAIL_L2");
0443   colNames.push_back("TBMA_TRAIL_L3");
0444   colNames.push_back("TBMA_TRAIL_L4");
0445   colNames.push_back("TBMA_HEAD_B");
0446   colNames.push_back("TBMA_HEAD_UB");
0447   colNames.push_back("TBMA_TRAIL_B");
0448   colNames.push_back("TBMA_TRAIL_UB");
0449   /*
0450   colNames.push_back("CONFIG_KEY_ID"           );
0451   colNames.push_back("CONFIG_KEY"              );
0452   colNames.push_back("VERSION"                 );
0453   colNames.push_back("CONDITION_DATA_SET_ID"   );
0454   colNames.push_back("KIND_OF_CONDITION_ID"    );
0455   colNames.push_back("KIND_OF_COND"            );
0456   colNames.push_back("PXLFED_NAME"             );
0457   colNames.push_back("FED_CHAN"                );
0458   colNames.push_back("TBM_PART_ID"             );
0459   colNames.push_back("TBM_SER_NUM"             );
0460   colNames.push_back("PANEL_NAME"              );
0461   colNames.push_back("HUB_ADDRS"               );
0462   colNames.push_back("TBMA_HEAD_L0"            );
0463   colNames.push_back("TBMA_HEAD_L1"            );
0464   colNames.push_back("TBMA_HEAD_L2"            );
0465   colNames.push_back("TBMA_HEAD_L3"            );
0466   colNames.push_back("TBMA_HEAD_L4"            );
0467   colNames.push_back("TBMA_TRAIL_L0"           );
0468   colNames.push_back("TBMA_TRAIL_L1"           );
0469   colNames.push_back("TBMA_TRAIL_L2"           );
0470   colNames.push_back("TBMA_TRAIL_L3"           );
0471   colNames.push_back("TBMA_TRAIL_L4"           );
0472 */
0473   // Retrieve header row and cross check that everyfield is there.
0474   for (unsigned int c = 0; c < ins.size(); c++) {
0475     for (unsigned int n = 0; n < colNames.size(); n++) {
0476       if (tableMat[firstRow][c] == colNames[n]) {
0477         colM[colNames[n]] = c;
0478         break;
0479       }
0480     }
0481   }  //end for
0482   for (unsigned int n = 0; n < colNames.size(); n++) {
0483     if (colM.find(colNames[n]) == colM.end()) {
0484       std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
0485       assert(0);
0486     }
0487   }
0488   for (int r = firstRow + 1; r < lastRow; r++)  //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
0489   {
0490     //Signal levels for the TBM, one per channel
0491     TBM_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L0"]].c_str());
0492     TBM_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L1"]].c_str());
0493     TBM_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L2"]].c_str());
0494     TBM_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L3"]].c_str());
0495     TBM_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L4"]].c_str());
0496     TRL_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L0"]].c_str());
0497     TRL_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L1"]].c_str());
0498     TRL_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L2"]].c_str());
0499     TRL_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L3"]].c_str());
0500     TRL_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L4"]].c_str());
0501   }
0502 }
0503
0504 void PixelFEDCard::readDBROCLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow) {
0505   string mthn = "[PixelFEDCard::readDBROCLevels()] ";
0506   map<string, int> colM;
0507   vector<string> colNames;
0508
0509   /**
0510      EXTERNAL_TABLE_NAME: ROC_ANALOG_LEVELS (VIEW: CONF_KEY_ROC_LEVELS_V)
0511
0512      CONFIG_KEY                    NOT NULL VARCHAR2(80)
0513      KEY_TYPE                      NOT NULL VARCHAR2(80)
0514      KEY_ALIAS                     NOT NULL VARCHAR2(80)
0515      VERSION                        VARCHAR2(40)
0516      KIND_OF_COND                  NOT NULL VARCHAR2(40)
0517      ROC_NAME                       VARCHAR2(200)
0518      FED_ROC_NUM                    NUMBER(38)
0519      PIXEL_FED                      NUMBER(38)
0520      FED_CHAN                       NUMBER(38)
0521      ROC_L0                    NOT NULL NUMBER(38) ROC_L0[1-36][1-21/24/8/16] indexes taken from FED_CHAN and FED_ROC_NUM respec.
0522      ROC_L1                    NOT NULL NUMBER(38) ROC_L1[1-36][1-21/24/8/16] indexes taken from FED_CHAN and FED_ROC_NUM respec.
0523      ROC_L2                    NOT NULL NUMBER(38) ROC_L2[1-36][1-21/24/8/16] indexes taken from FED_CHAN and FED_ROC_NUM respec.
0524      ROC_L3                    NOT NULL NUMBER(38) ROC_L3[1-36][1-21/24/8/16] indexes taken from FED_CHAN and FED_ROC_NUM respec.
0525      ROC_L4                    NOT NULL NUMBER(38) ROC_L4[1-36][1-21/24/8/16] indexes taken from FED_CHAN and FED_ROC_NUM respec.
0526      ROC_B                      NUMBER(38)
0527      ROC_UB                     NUMBER(38)
0528
0529   */
0530
0531   colNames.push_back("CONFIG_KEY");
0532   colNames.push_back("KEY_TYPE");
0533   colNames.push_back("KEY_ALIAS");
0534   colNames.push_back("VERSION");
0535   colNames.push_back("KIND_OF_COND");
0536   colNames.push_back("ROC_NAME");
0537   colNames.push_back("FED_ROC_NUM");
0538   colNames.push_back("PIXEL_FED");
0539   colNames.push_back("FED_CHAN");
0540   colNames.push_back("ROC_L0");
0541   colNames.push_back("ROC_L1");
0542   colNames.push_back("ROC_L2");
0543   colNames.push_back("ROC_L3");
0544   colNames.push_back("ROC_L4");
0545   colNames.push_back("ROC_B");
0546   colNames.push_back("ROC_UB");
0547   /*
0548   colNames.push_back("CONFIG_KEY_ID"    );
0549   colNames.push_back("CONFIG_KEY"       );
0550   colNames.push_back("VERSION"          );
0551   colNames.push_back("KIND_OF_COND"     );
0552   colNames.push_back("PXLFED_NAME"      );
0553   colNames.push_back("FED_CHAN"         );
0554   colNames.push_back("AOH_CHAN"         );
0555   colNames.push_back("ROC_NAME"         );
0556   colNames.push_back("HUB_ADDRS"        );
0557   colNames.push_back("PORT_NUMBER"      );
0558   colNames.push_back("ROC_I2C_ADDR"     );
0559   colNames.push_back("GEOM_ROC_NUM"     );
0560   colNames.push_back("FED_ROC_NUM"      );
0561   colNames.push_back("ROC_L0"           );
0562   colNames.push_back("ROC_L1"           );
0563   colNames.push_back("ROC_L2"           );
0564   colNames.push_back("ROC_L3"           );
0565   colNames.push_back("ROC_L4"           );
0566 */
0567   // Retrieve header row and cross check that everyfield is there.
0568   for (unsigned int c = 0; c < tableMat[firstRow].size(); c++) {
0569     for (unsigned int n = 0; n < colNames.size(); n++) {
0570       if (tableMat[firstRow][c] == colNames[n]) {
0571         colM[colNames[n]] = c;
0572         break;
0573       }
0574     }
0575   }  //end for
0576   for (unsigned int n = 0; n < colNames.size(); n++) {
0577     if (colM.find(colNames[n]) == colM.end()) {
0578       std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
0579       assert(0);
0580     }
0581   }
0582   // Address levels 1 per channel (36) per roc(max=26)
0583   //   int ROC_L0[36][26],ROC_L1[36][26],ROC_L2[36][26],ROC_L3[36][26],ROC_L4[36][26];
0584
0585   for (int r = firstRow + 1; r < lastRow; r++)  //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
0586   {
0587     ROC_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
0588         atoi(tableMat[r][colM["ROC_L0"]].c_str());
0589     ROC_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
0590         atoi(tableMat[r][colM["ROC_L1"]].c_str());
0591     ROC_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
0592         atoi(tableMat[r][colM["ROC_L2"]].c_str());
0593     ROC_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
0594         atoi(tableMat[r][colM["ROC_L3"]].c_str());
0595     ROC_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
0596         atoi(tableMat[r][colM["ROC_L4"]].c_str());
0597   }
0598 }
0599
0600 // Read the configuration parameters from file
0601 PixelFEDCard::PixelFEDCard(string fileName) : PixelConfigBase(" ", " ", " ") {
0602   std::string mthn = "]\t[PixelFEDCard::PixelFEDCard()]\t\t\t\t    ";
0603   //const bool localDEBUG = true;
0604   const bool localDEBUG = false;
0605
0606   // Added by Dario (March 26th, 2008): insure variables are all cleared before read-in
0607   clear();
0608
0609   //  cout << __LINE__ << "]\t" << mthn <<" Get setup parameters from file "<<fileName<<endl;
0610   FILE *infile = fopen((fileName.c_str()), "r");
0611   if (infile == nullptr)
0612     throw std::runtime_error("Failed to open FED Card parameter file: " + fileName);
0613
0614   //Fed Base Address
0615   fscanf(infile, "FED Base address                         :%lx\n", &FEDBASE_0);
0616   fscanf(infile, "FEDID Number                             :%lx\n", &fedNumber);
0617
0618   //  if(localDEBUG) cout << __LINE__ << mthn << "FED Base address, FED # : " << std::hex << FEDBASE_0 << std::dec << std::endl ;
0619   //  if(localDEBUG) printf("FED Base address, FED # :%lx\n",FEDBASE_0);
0620   //if(FEDBASE != FEDBASE_0) cout<< __LINE__ << "]\t" << mthn << " Inconsistent FED base address?"<<endl;
0621   //  if(localDEBUG) cout << __LINE__ << mthn << "FEDID #                 : " << std::hex << fedNumber << std::dec << std::endl ;
0622   //  if(localDEBUG) printf("FEDID # :%lx\n",fedNumber);
0623
0624   // Number of ROCs
0625   int ijx = 0;
0626   for (int i = 0; i < 36; i++) {
0627     ijx = i + 1;
0628     fscanf(infile, "Number of ROCs Chnl %d:%d \n", &ijx, &NRocs[i]);
0629     if (localDEBUG)
0630       printf("Number of ROCs per Chnl %d:%d \n", ijx, NRocs[i]);
0631   }
0632
0633   //Settable optical input parameters
0634   fscanf(infile, "Optical reciever 1  Capacitor Adjust(0-3):%d\n", &opt_cap[0]);
0635   fscanf(infile, "Optical reciever 2  Capacitor Adjust(0-3):%d\n", &opt_cap[1]);
0636   fscanf(infile, "Optical reciever 3  Capacitor Adjust(0-3):%d\n", &opt_cap[2]);
0637   fscanf(infile, "Optical reciever 1  Input Offset (0-15)  :%d\n", &opt_inadj[0]);
0638   fscanf(infile, "Optical reciever 2  Input Offset (0-15)  :%d\n", &opt_inadj[1]);
0639   fscanf(infile, "Optical reciever 3  Input Offset (0-15)  :%d\n", &opt_inadj[2]);
0640   fscanf(infile, "Optical reciever 1 Output Offset (0-3)   :%d\n", &opt_ouadj[0]);
0641   fscanf(infile, "Optical reciever 2 Output Offset (0-3)   :%d\n", &opt_ouadj[1]);
0642   fscanf(infile, "Optical reciever 3 Output Offset (0-3)   :%d\n", &opt_ouadj[2]);
0643
0644   if (localDEBUG) {
0645     printf("Optical reciever 1  Capacitor Adjust(0-3):%d\n", opt_cap[0]);
0646     printf("Optical reciever 2  Capacitor Adjust(0-3):%d\n", opt_cap[1]);
0647     printf("Optical reciever 3  Capacitor Adjust(0-3):%d\n", opt_cap[2]);
0648     printf("Optical reciever 1  Input Offset (0-15)  :%d\n", opt_inadj[0]);
0649     printf("Optical reciever 2  Input Offset (0-15)  :%d\n", opt_inadj[1]);
0650     printf("Optical reciever 3  Input Offset (0-15)  :%d\n", opt_inadj[2]);
0651     printf("Optical reciever 1 Output Offset (0-3)   :%d\n", opt_ouadj[0]);
0652     printf("Optical reciever 2 Output Offset (0-3)   :%d\n", opt_ouadj[1]);
0653     printf("Optical reciever 3 Output Offset (0-3)   :%d\n", opt_ouadj[2]);
0654   }
0655
0656   //input offset dac
0657   for (int i = 0; i < 36; i++) {
0658     fscanf(infile, "Offset DAC channel %d:%d\n", &ijx, &offs_dac[i]);
0659     if (localDEBUG)
0660       printf("Offset DAC channel %d:%d\n", i + 1, offs_dac[i]);
0661   }
0662
0663   //clock phases
0664   fscanf(infile, "Clock Phase Bits ch   1-9:%x\n", &clkphs1_9);
0665   fscanf(infile, "Clock Phase Bits ch 10-18:%x\n", &clkphs10_18);
0666   fscanf(infile, "Clock Phase Bits ch 19-27:%x\n", &clkphs19_27);
0667   fscanf(infile, "Clock Phase Bits ch 28-36:%x\n", &clkphs28_36);
0668   if (localDEBUG)
0669     printf("Clock Phase Bits ch    1-9:%x\n", clkphs1_9);
0670   if (localDEBUG)
0671     printf("Clock Phase Bits ch  10-18:%x\n", clkphs10_18);
0672   if (localDEBUG)
0673     printf("Clock Phase Bits ch  19-27:%x\n", clkphs19_27);
0674   if (localDEBUG)
0675     printf("Clock Phase Bits ch  28-36:%x\n", clkphs28_36);
0676
0677   //Blacks
0678   for (int i = 0; i < 36; i++) {
0679     fscanf(infile, "Black HiThold ch %d:%d \n", &ijx, &BlackHi[i]);
0680     fscanf(infile, "Black LoThold ch %d:%d \n", &ijx, &BlackLo[i]);
0681     fscanf(infile, "ULblack Thold ch %d:%d \n", &ijx, &Ublack[i]);
0682     if (localDEBUG)
0683       printf("Black HiThold ch %d:%d\n", ijx, BlackHi[i]);
0684     if (localDEBUG)
0685       printf("Black LoThold ch %d:%d\n", ijx, BlackLo[i]);
0686     if (localDEBUG)
0687       printf("ULblack Thold ch %d:%d\n", ijx, Ublack[i]);
0688   }
0689
0690   //Channel delays
0691   for (int i = 0; i < 36; i++) {
0692     fscanf(infile, "Delay channel %d(0-15):%d\n", &ijx, &DelayCh[i]);
0693     if (localDEBUG)
0694       printf("Delay channel %d(0-15):%d\n", i + 1, DelayCh[i]);
0695   }
0696
0697   //Signal levels
0698   for (int i = 0; i < 36; i++) {
0699     fscanf(infile, "TBM level 0 Channel  %d:%d\n", &ijx, &TBM_L0[i]);
0700     fscanf(infile, "TBM level 1 Channel  %d:%d\n", &ijx, &TBM_L1[i]);
0701     fscanf(infile, "TBM level 2 Channel  %d:%d\n", &ijx, &TBM_L2[i]);
0702     fscanf(infile, "TBM level 3 Channel  %d:%d\n", &ijx, &TBM_L3[i]);
0703     fscanf(infile, "TBM level 4 Channel  %d:%d\n", &ijx, &TBM_L4[i]);
0704     if (localDEBUG)
0705       printf("TBM level 0 Channel  %d:%d\n", ijx, TBM_L0[i]);
0706     if (localDEBUG)
0707       printf("TBM level 1 Channel  %d:%d\n", ijx, TBM_L1[i]);
0708     if (localDEBUG)
0709       printf("TBM level 2 Channel  %d:%d\n", ijx, TBM_L2[i]);
0710     if (localDEBUG)
0711       printf("TBM level 3 Channel  %d:%d\n", ijx, TBM_L3[i]);
0712     if (localDEBUG)
0713       printf("TBM level 4 Channel  %d:%d\n", ijx, TBM_L4[i]);
0714
0715     int ijy = 0;
0716     for (int j = 0; j < NRocs[i]; j++) {
0717       fscanf(infile, "ROC%d level 0 Channel  %d :%d\n", &ijy, &ijx, &ROC_L0[i][j]);
0718       fscanf(infile, "ROC%d level 1 Channel  %d :%d\n", &ijy, &ijx, &ROC_L1[i][j]);
0719       fscanf(infile, "ROC%d level 2 Channel  %d :%d\n", &ijy, &ijx, &ROC_L2[i][j]);
0720       fscanf(infile, "ROC%d level 3 Channel  %d :%d\n", &ijy, &ijx, &ROC_L3[i][j]);
0721       fscanf(infile, "ROC%d level 4 Channel  %d :%d\n", &ijy, &ijx, &ROC_L4[i][j]);
0722       if (localDEBUG)
0723         printf("ROC%d level 0 Channel  %d :%d\n", ijy, ijx, ROC_L0[i][j]);
0724       if (localDEBUG)
0725         printf("ROC%d level 1 Channel  %d :%d\n", ijy, ijx, ROC_L1[i][j]);
0726       if (localDEBUG)
0727         printf("ROC%d level 2 Channel  %d :%d\n", ijy, ijx, ROC_L2[i][j]);
0728       if (localDEBUG)
0729         printf("ROC%d level 3 Channel  %d :%d\n", ijy, ijx, ROC_L3[i][j]);
0730       if (localDEBUG)
0731         printf("ROC%d level 4 Channel  %d :%d\n", ijy, ijx, ROC_L4[i][j]);
0732     }
0733
0734     fscanf(infile, "TRLR level 0 Channel %d:%d\n", &ijx, &TRL_L0[i]);
0735     fscanf(infile, "TRLR level 1 Channel %d:%d\n", &ijx, &TRL_L1[i]);
0736     fscanf(infile, "TRLR level 2 Channel %d:%d\n", &ijx, &TRL_L2[i]);
0737     fscanf(infile, "TRLR level 3 Channel %d:%d\n", &ijx, &TRL_L3[i]);
0738     fscanf(infile, "TRLR level 4 Channel %d:%d\n", &ijx, &TRL_L4[i]);
0739     if (localDEBUG)
0740       printf("TRLR level 0 Channel %d:%d\n", ijx, TRL_L0[i]);
0741     if (localDEBUG)
0742       printf("TRLR level 1 Channel %d:%d\n", ijx, TRL_L1[i]);
0743     if (localDEBUG)
0744       printf("TRLR level 2 Channel %d:%d\n", ijx, TRL_L2[i]);
0745     if (localDEBUG)
0746       printf("TRLR level 3 Channel %d:%d\n", ijx, TRL_L3[i]);
0747     if (localDEBUG)
0748       printf("TRLR level 4 Channel %d:%d\n", ijx, TRL_L4[i]);
0749   }
0750
0751   //These bits turn off(1) and on(0) channels
0752   fscanf(infile, "Channel Enbable bits chnls 1-9  (on = 0):%x\n", &Ncntrl);
0753   fscanf(infile, "Channel Enbable bits chnls 10-18(on = 0):%x\n", &NCcntrl);
0754   fscanf(infile, "Channel Enbable bits chnls 19-27(on = 0):%x\n", &SCcntrl);
0755   fscanf(infile, "Channel Enbable bits chnls 28-36(on = 0):%x\n", &Scntrl);
0756   if (localDEBUG)
0757     printf("Channel Enbable bits chnls 1-9  (on = 0):%x\n", Ncntrl);
0758   if (localDEBUG)
0759     printf("Channel Enbable bits chnls 10-18(on = 0):%x\n", NCcntrl);
0760   if (localDEBUG)
0761     printf("Channel Enbable bits chnls 19-27(on = 0):%x\n", SCcntrl);
0762   if (localDEBUG)
0763     printf("Channel Enbable bits chnls 28-36(on = 0):%x\n", Scntrl);
0764
0765   //These are delays to the TTCrx
0766   fscanf(infile, "TTCrx Coarse Delay Register 2:%d\n", &CoarseDel);
0767   fscanf(infile, "TTCrc      ClkDes2 Register 3:%x\n", &ClkDes2);
0768   fscanf(infile, "TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", &FineDes2Del);
0769   if (localDEBUG)
0770     printf("TTCrx Coarse Delay Register 2:%d\n", CoarseDel);
0771   if (localDEBUG)
0772     printf("TTCrc      ClkDes2 Register 3:%x\n", ClkDes2);
0773   if (localDEBUG)
0774     printf("TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", FineDes2Del);
0775
0776   // Control register
0777   fscanf(infile, "Center Chip Control Reg:%x\n", &Ccntrl);
0778   if (localDEBUG)
0779     printf("Control Reg:0x%x\n", Ccntrl);
0780   fscanf(infile, "Initial Slink DAQ mode:%d\n", &modeRegister);
0781   if (localDEBUG)
0782     printf("Mode Reg:%d\n", modeRegister);
0783
0784   //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
0785   fscanf(infile, "Channel ADC Gain bits chnls  1-12(1Vpp = 0):%x\n", &Nadcg);
0786   fscanf(infile, "Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n", &NCadcg);
0787   fscanf(infile, "Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n", &SCadcg);
0788   fscanf(infile, "Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n", &Sadcg);
0789   if (localDEBUG)
0790     printf("Channel ADC Gain bits chnls  1-12(1Vpp = 0):%x\n", Nadcg);
0791   if (localDEBUG)
0792     printf("Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n", NCadcg);
0793   if (localDEBUG)
0794     printf("Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n", SCadcg);
0795   if (localDEBUG)
0796     printf("Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n", Sadcg);
0797
0798   //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
0799   fscanf(infile, "Channel Baseline Enbable chnls 1-9  (on = (0x1ff<<16)+):%x\n", &Nbaseln);
0800   fscanf(infile, "Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n", &NCbaseln);
0801   fscanf(infile, "Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n", &SCbaseln);
0802   fscanf(infile, "Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n", &Sbaseln);
0803   if (localDEBUG)
0804     printf("Channel Baseline Enbable chnls 1-9  (on = (0x1ff<<16)+):%x\n", Nbaseln);
0805   if (localDEBUG)
0806     printf("Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n", NCbaseln);
0807   if (localDEBUG)
0808     printf("Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n", SCbaseln);
0809   if (localDEBUG)
0810     printf("Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n", Sbaseln);
0811
0812   //These bits set TBM trailer mask (common by FPGA)
0813   fscanf(infile, "TBM trailer mask chnls 1-9  (0xff = all masked):%x\n", &N_TBMmask);
0814   fscanf(infile, "TBM trailer mask chnls 10-18(0xff = all masked):%x\n", &NC_TBMmask);
0815   fscanf(infile, "TBM trailer mask chnls 19-27(0xff = all masked):%x\n", &SC_TBMmask);
0816   fscanf(infile, "TBM trailer mask chnls 28-36(0xff = all masked):%x\n", &S_TBMmask);
0817   if (localDEBUG)
0818     printf("TBM trailer mask chnls 1-9  (0xff = all masked):%x\n", N_TBMmask);
0819   if (localDEBUG)
0820     printf("TBM trailer mask chnls 10-18(0xff = all masked):%x\n", NC_TBMmask);
0821   if (localDEBUG)
0822     printf("TBM trailer mask chnls 19-27(0xff = all masked):%x\n", SC_TBMmask);
0823   if (localDEBUG)
0824     printf("TBM trailer mask chnls 28-36(0xff = all masked):%x\n", S_TBMmask);
0825
0826   //These bits set the Private fill/gap word value (common by FPGA)
0827   fscanf(infile, "Private 8 bit word chnls 1-9  :%x\n", &N_Pword);
0828   fscanf(infile, "Private 8 bit word chnls 10-18:%x\n", &NC_Pword);
0829   fscanf(infile, "Private 8 bit word chnls 19-27:%x\n", &SC_Pword);
0830   fscanf(infile, "Private 8 bit word chnls 28-36:%x\n", &S_Pword);
0831   if (localDEBUG)
0832     printf("Private 8 bit word chnls 1-9  :%x\n", N_Pword);
0833   if (localDEBUG)
0834     printf("Private 8 bit word chnls 10-18:%x\n", NC_Pword);
0835   if (localDEBUG)
0836     printf("Private 8 bit word chnls 19-27:%x\n", SC_Pword);
0837   if (localDEBUG)
0838     printf("Private 8 bit word chnls 28-36:%x\n", S_Pword);
0839
0840   //These bit sets the special dac mode for random triggers
0841   fscanf(infile, "Special Random testDAC mode (on = 0x1, off=0x0):%x\n", &SpecialDac);
0842   if (localDEBUG)
0843     printf("Special Random testDAC mode (on = 0x1, off=0x0):%x\n", SpecialDac);
0844
0845   //These bits set the number of Out of consecutive out of sync events until a TTs OOs
0846   fscanf(infile, "Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", &Ooslvl);
0847   if (localDEBUG)
0848     printf("Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", Ooslvl);
0849
0850   //These bits set the number of Empty events until a TTs Error
0851   fscanf(infile, "Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", &Errlvl);
0852   if (localDEBUG)
0853     printf("Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", Errlvl);
0854
0855   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
0856   fscanf(infile, "N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &Nfifo1Bzlvl);
0857   if (localDEBUG)
0858     printf("N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Nfifo1Bzlvl);
0859
0860   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
0861   fscanf(infile, "NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &NCfifo1Bzlvl);
0862   if (localDEBUG)
0863     printf("NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", NCfifo1Bzlvl);
0864
0865   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
0866   fscanf(infile, "SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &SCfifo1Bzlvl);
0867   if (localDEBUG)
0868     printf("SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", SCfifo1Bzlvl);
0869
0870   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
0871   fscanf(infile, "S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &Sfifo1Bzlvl);
0872   if (localDEBUG)
0873     printf("S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Sfifo1Bzlvl);
0874
0875   //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
0876   fscanf(infile, "Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", &fifo3Wrnlvl);
0877   if (localDEBUG)
0878     printf("Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", fifo3Wrnlvl);
0879
0880   fscanf(infile, "FED Master delay 0=0,1=32,2=48,3=64:%d\n", &FedTTCDelay);
0881   if (localDEBUG)
0882     printf("FED Master delay 0=0,1=32,2=48,3=64:%d\n", FedTTCDelay);
0883
0884   fscanf(infile, "TTCrx Register 0 fine delay ClkDes1:%d\n", &FineDes1Del);
0885   if (localDEBUG)
0886     printf("TTCrx Register 0 fine delay ClkDes1:%d\n", FineDes1Del);
0887
0888   int checkword = 0;
0889   fscanf(infile, "Params FED file check word:%d\n", &checkword);
0890   if (checkword != 90508 && checkword != 91509 && checkword != 20211)
0891     cout << __LINE__ << "]\t" << mthn << "FEDID: " << fedNumber << " Params FED File read error. Checkword read "
0892          << checkword << " check word expected 090508 or 91509 or 20211" << endl;
0893   assert((checkword == 90508) | (checkword == 91509) | (checkword == 20211));
0894
0895   if (localDEBUG)
0896     cout << __LINE__ << "]\t" << mthn << "Params FED file check word: " << checkword << endl;
0897
0898   //These bits set the hit limit in fifo-1 for an event
0899
0900   if (checkword == 20211) {
0901     //These bits set the hit limit in fifo-1 for an event
0902     fscanf(infile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &N_hitlimit);
0903     if (localDEBUG)
0904       printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", N_hitlimit);
0905     fscanf(infile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &NC_hitlimit);
0906     if (localDEBUG)
0907       printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", NC_hitlimit);
0908     fscanf(infile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &SC_hitlimit);
0909     if (localDEBUG)
0910       printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", SC_hitlimit);
0911     fscanf(infile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &S_hitlimit);
0912     if (localDEBUG)
0913       printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", S_hitlimit);
0914     //These bits allow a ROC to be skipped (1/fpga)
0915
0916     fscanf(infile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &N_testreg);
0917     if (localDEBUG)
0918       printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
0919     fscanf(infile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &NC_testreg);
0920     if (localDEBUG)
0921       printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
0922     fscanf(infile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &SC_testreg);
0923     if (localDEBUG)
0924       printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
0925     fscanf(infile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &S_testreg);
0926     if (localDEBUG)
0927       printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
0928
0929     fscanf(infile, "Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", &BusyWhenBehind);
0930     if (localDEBUG)
0931       printf("Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", BusyWhenBehind);
0932
0933     fscanf(infile, "D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n", &FeatureRegister);
0934     if (localDEBUG)
0935       printf("D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n", FeatureRegister);
0936
0937     fscanf(infile, "Limit for fifo-2 almost full (point for the TTS flag):%x\n", &FIFO2Limit);
0938     if (localDEBUG)
0939       printf("Limit for fifo-2 almost full (point for the TTS flag):%x\n", FIFO2Limit);
0940
0941     fscanf(infile, "Limit for consecutive timeout OR OOSs:%d\n", &TimeoutOROOSLimit);
0942     if (localDEBUG)
0943       printf("Limit for consecutive timeout OR OOSs:%d\n", TimeoutOROOSLimit);
0944
0945     fscanf(infile, "Turn off filling of lastdac fifos(exc 1st ROC):%d\n", &LastDacOff);
0946     if (localDEBUG)
0947       printf("Turn off filling of lastdac fifos(exc 1st ROC):%d\n", LastDacOff);
0948
0949     fscanf(infile, "Number of simulated hits per ROC for internal generator:%d\n", &SimHitsPerRoc);
0950     if (localDEBUG)
0951       printf("Number of simulated hits per ROC for internal generator:%d\n", SimHitsPerRoc);
0952
0953     fscanf(infile, "Miniumum hold time for busy (changing definition):%d\n", &BusyHoldMin);
0954     if (localDEBUG)
0955       printf("Miniumum hold time for busy (changing definition):%d\n", BusyHoldMin);
0956
0957     fscanf(infile, "Trigger Holdoff in units of 25us(0=none):%d\n", &TriggerHoldoff);
0958     if (localDEBUG)
0959       printf("Trigger Holdoff in units of 25us(0=none):%d\n", TriggerHoldoff);
0960
0961     fscanf(infile, "Spare fedcard input 1:%d\n", &SPARE1);
0962     if (localDEBUG)
0963       printf("Spare fedcard input 1:%d\n", SPARE1);
0964     fscanf(infile, "Spare fedcard input 2:%d\n", &SPARE2);
0965     if (localDEBUG)
0966       printf("Spare fedcard input 2:%d\n", SPARE2);
0967     fscanf(infile, "Spare fedcard input 3:%d\n", &SPARE3);
0968     if (localDEBUG)
0969       printf("Spare fedcard input 3:%d\n", SPARE3);
0970     fscanf(infile, "Spare fedcard input 4:%d\n", &SPARE4);
0971     if (localDEBUG)
0972       printf("Spare fedcard input 4:%d\n", SPARE4);
0973     fscanf(infile, "Spare fedcard input 5:%d\n", &SPARE5);
0974     if (localDEBUG)
0975       printf("Spare fedcard input 5:%d\n", SPARE5);
0976     fscanf(infile, "Spare fedcard input 6:%d\n", &SPARE6);
0977     if (localDEBUG)
0978       printf("Spare fedcard input 6:%d\n", SPARE6);
0979     fscanf(infile, "Spare fedcard input 7:%d\n", &SPARE7);
0980     if (localDEBUG)
0981       printf("Spare fedcard input 7:%d\n", SPARE7);
0982     fscanf(infile, "Spare fedcard input 8:%d\n", &SPARE8);
0983     if (localDEBUG)
0984       printf("Spare fedcard input 8:%d\n", SPARE8);
0985     fscanf(infile, "Spare fedcard input 9:%d\n", &SPARE9);
0986     if (localDEBUG)
0987       printf("Spare fedcard input 9:%d\n", SPARE9);
0988     fscanf(infile, "Spare fedcard input 10:%d\n", &SPARE10);
0989     if (localDEBUG)
0990       printf("Spare fedcard input 10:%d\n", SPARE10);
0991
0992   } else if (checkword == 91509) {
0993     //These bits set the hit limit in fifo-1 for an event
0994     fscanf(infile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &N_hitlimit);
0995     if (localDEBUG)
0996       printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", N_hitlimit);
0997     fscanf(infile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &NC_hitlimit);
0998     if (localDEBUG)
0999       printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", NC_hitlimit);
1000     fscanf(infile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &SC_hitlimit);
1001     if (localDEBUG)
1002       printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", SC_hitlimit);
1003     fscanf(infile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &S_hitlimit);
1004     if (localDEBUG)
1005       printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", S_hitlimit);
1006     //These bits allow a ROC to be skipped (1/fpga)
1007
1008     fscanf(infile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &N_testreg);
1009     if (localDEBUG)
1010       printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
1011     fscanf(infile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &NC_testreg);
1012     if (localDEBUG)
1013       printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
1014     fscanf(infile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &SC_testreg);
1015     if (localDEBUG)
1016       printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
1017     fscanf(infile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &S_testreg);
1018     if (localDEBUG)
1019       printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
1020
1021     BusyWhenBehind = 8;
1022     FeatureRegister = 0x1;
1023     FIFO2Limit = 0x1C00;
1024     TimeoutOROOSLimit = 200;
1025     LastDacOff = 0;
1026     SimHitsPerRoc = 0;
1027     BusyHoldMin = 0;
1028     TriggerHoldoff = 0;
1029     SPARE1 = 0;
1030     SPARE2 = 0;
1031     SPARE3 = 0;
1032     SPARE4 = 0;
1033     SPARE5 = 0;
1034     SPARE6 = 0;
1035     SPARE7 = 0;
1036     SPARE8 = 0;
1037     SPARE9 = 0;
1038     SPARE10 = 0;
1039
1040   } else {
1041     N_hitlimit = 192;
1042     NC_hitlimit = 192;
1043     SC_hitlimit = 192;
1044     S_hitlimit = 192;
1045
1046     N_testreg = 0;
1047     NC_testreg = 0;
1048     SC_testreg = 0;
1049     S_testreg = 0;
1050
1051     BusyWhenBehind = 8;
1052     FeatureRegister = 0x1;
1053     FIFO2Limit = 0x1c00;
1054     TimeoutOROOSLimit = 200;
1055     LastDacOff = 0;
1056     SimHitsPerRoc = 0;
1057     BusyHoldMin = 0;
1058     TriggerHoldoff = 0;
1059     SPARE1 = 0;
1060     SPARE2 = 0;
1061     SPARE3 = 0;
1062     SPARE4 = 0;
1063     SPARE5 = 0;
1064     SPARE6 = 0;
1065     SPARE7 = 0;
1066     SPARE8 = 0;
1067     SPARE9 = 0;
1068     SPARE10 = 0;
1069   }
1070
1071   fclose(infile);
1072
1073   Ccntrl_original = Ccntrl;
1074   modeRegister_original = modeRegister;
1075
1076   Ncntrl_original = Ncntrl;
1077   NCcntrl_original = NCcntrl;
1078   SCcntrl_original = SCcntrl;
1079   Scntrl_original = Scntrl;
1080
1081   Nbaseln_original = Nbaseln;
1082   NCbaseln_original = NCbaseln;
1083   SCbaseln_original = SCbaseln;
1084   Sbaseln_original = Sbaseln;
1085
1086   return;
1087 }
1088
1089 //==================================================================================
1090 // Added by Dario (March 26th 2008)
1091 void PixelFEDCard::clear(void) {
1092   FEDBASE_0 = 0;
1093   fedNumber = 999;
1094   for (int i = 0; i < 36; i++) {
1095     NRocs[i] = 0;
1096     offs_dac[i] = 0;
1097     BlackHi[i] = 0;
1098     BlackLo[i] = 0;
1099     Ublack[i] = 0;
1100     DelayCh[i] = 0;
1101     TBM_L0[i] = 0;
1102     TBM_L1[i] = 0;
1103     TBM_L2[i] = 0;
1104     TBM_L3[i] = 0;
1105     TBM_L4[i] = 0;
1106     TRL_L0[i] = 0;
1107     TRL_L1[i] = 0;
1108     TRL_L2[i] = 0;
1109     TRL_L3[i] = 0;
1110     TRL_L4[i] = 0;
1111   }
1112   for (int i = 0; i < 3; i++) {
1113     opt_cap[i] = 0;
1114     opt_inadj[i] = 0;
1115     opt_ouadj[i] = 0;
1116   }
1117   clkphs1_9 = 0;
1118   clkphs10_18 = 0;
1119   clkphs19_27 = 0;
1120   clkphs28_36 = 0;
1121
1122   for (int i = 0; i < 36; i++) {
1123     for (int j = 0; j < 26; j++) {
1124       ROC_L0[i][j] = 0;
1125       ROC_L1[i][j] = 0;
1126       ROC_L2[i][j] = 0;
1127       ROC_L3[i][j] = 0;
1128       ROC_L4[i][j] = 0;
1129     }
1130   }
1131   Ncntrl = 0;
1132   NCcntrl = 0;
1133   SCcntrl = 0;
1134   Scntrl = 0;
1135   CoarseDel = 0;
1136   ClkDes2 = 0;
1137   FineDes2Del = 0;
1138   FineDes1Del = 0;
1139   Ccntrl = 0;
1140   modeRegister = 0;
1141   Nadcg = 0;
1142   NCadcg = 0;
1143   SCadcg = 0;
1144   Sadcg = 0;
1145   Nbaseln = 0;
1146   NCbaseln = 0;
1147   SCbaseln = 0;
1148   Sbaseln = 0;
1149   N_TBMmask = 0;
1150   NC_TBMmask = 0;
1151   SC_TBMmask = 0;
1152   S_TBMmask = 0;
1153   N_Pword = 0;
1154   NC_Pword = 0;
1155   SC_Pword = 0;
1156   S_Pword = 0;
1157   SpecialDac = 0;
1158   Ooslvl = 0;
1159   Errlvl = 0;
1160   Nfifo1Bzlvl = 0;
1161   NCfifo1Bzlvl = 0;
1162   SCfifo1Bzlvl = 0;
1163   Sfifo1Bzlvl = 0;
1164   fifo3Wrnlvl = 0;
1165
1166   BusyHoldMin = 0;
1167   BusyWhenBehind = 0;
1168   FeatureRegister = 0;
1169   FIFO2Limit = 0;
1170   LastDacOff = 0;
1171   SimHitsPerRoc = 0;
1172   TimeoutOROOSLimit = 0;
1173   TriggerHoldoff = 0;
1174
1175   SPARE1 = 0;
1176   SPARE2 = 0;
1177   SPARE3 = 0;
1178   SPARE4 = 0;
1179   SPARE5 = 0;
1180   SPARE6 = 0;
1181   SPARE7 = 0;
1182   SPARE8 = 0;
1183   SPARE9 = 0;
1184   SPARE10 = 0;
1185 }
1186 //==================================================================================
1187
1188 void PixelFEDCard::writeASCII(std::string dir) const {
1189   std::string mthn = "[PixelFEDCard::writeASCII()]\t\t\t\t    ";
1190
1191   ostringstream s1;
1192   s1 << fedNumber;
1193   std::string fedNum = s1.str();
1194
1195   if (!dir.empty())
1196     dir += "/";
1197
1198   std::string filename = dir + "params_fed_" + fedNum + ".dat";
1199
1200   FILE *outfile = fopen((filename.c_str()), "w");
1201   if (outfile == nullptr) {
1202     cout << __LINE__ << "]\t" << mthn << "Could not open file: " << filename << " for writing" << endl;
1203     return;
1204   }
1205
1206   //Fed Base Address
1207   fprintf(outfile, "FED Base address                         :0x%lx\n", FEDBASE_0);
1208   fprintf(outfile, "FEDID Number                             :0x%lx\n", fedNumber);
1209
1210   // Number of ROCs
1211   int ijx = 0;
1212   for (int i = 0; i < 36; i++) {
1213     ijx = i + 1;
1214     fprintf(outfile, "Number of ROCs Chnl %d:%d\n", ijx, NRocs[i]);
1215   }
1216
1217   //Settable optical input parameters
1218   fprintf(outfile, "Optical reciever 1  Capacitor Adjust(0-3):%d\n", opt_cap[0]);
1219   fprintf(outfile, "Optical reciever 2  Capacitor Adjust(0-3):%d\n", opt_cap[1]);
1220   fprintf(outfile, "Optical reciever 3  Capacitor Adjust(0-3):%d\n", opt_cap[2]);
1221   fprintf(outfile, "Optical reciever 1  Input Offset (0-15)  :%d\n", opt_inadj[0]);
1222   fprintf(outfile, "Optical reciever 2  Input Offset (0-15)  :%d\n", opt_inadj[1]);
1223   fprintf(outfile, "Optical reciever 3  Input Offset (0-15)  :%d\n", opt_inadj[2]);
1224   fprintf(outfile, "Optical reciever 1 Output Offset (0-3)   :%d\n", opt_ouadj[0]);
1225   fprintf(outfile, "Optical reciever 2 Output Offset (0-3)   :%d\n", opt_ouadj[1]);
1226   fprintf(outfile, "Optical reciever 3 Output Offset (0-3)   :%d\n", opt_ouadj[2]);
1227
1228   //input offset dac
1229   for (int i = 0; i < 36; i++) {
1230     fprintf(outfile, "Offset DAC channel %d:%d\n", i + 1, offs_dac[i]);
1231   }
1232
1233   //clock phases
1234   fprintf(outfile, "Clock Phase Bits ch   1-9:0x%x\n", clkphs1_9);
1235   fprintf(outfile, "Clock Phase Bits ch 10-18:0x%x\n", clkphs10_18);
1236   fprintf(outfile, "Clock Phase Bits ch 19-27:0x%x\n", clkphs19_27);
1237   fprintf(outfile, "Clock Phase Bits ch 28-36:0x%x\n", clkphs28_36);
1238
1239   //Blacks
1240   for (int i = 0; i < 36; i++) {
1241     fprintf(outfile, "Black HiThold ch %d:%d \n", i + 1, BlackHi[i]);
1242     fprintf(outfile, "Black LoThold ch %d:%d \n", i + 1, BlackLo[i]);
1243     fprintf(outfile, "ULblack Thold ch %d:%d \n", i + 1, Ublack[i]);
1244   }
1245
1246   //Channel delays
1247   for (int i = 0; i < 36; i++) {
1248     fprintf(outfile, "Delay channel %d(0-15):%d\n", i + 1, DelayCh[i]);
1249   }
1250
1251   //Signal levels
1252   for (int i = 0; i < 36; i++) {
1253     fprintf(outfile, "TBM level 0 Channel  %d:%d\n", i + 1, TBM_L0[i]);
1254     fprintf(outfile, "TBM level 1 Channel  %d:%d\n", i + 1, TBM_L1[i]);
1255     fprintf(outfile, "TBM level 2 Channel  %d:%d\n", i + 1, TBM_L2[i]);
1256     fprintf(outfile, "TBM level 3 Channel  %d:%d\n", i + 1, TBM_L3[i]);
1257     fprintf(outfile, "TBM level 4 Channel  %d:%d\n", i + 1, TBM_L4[i]);
1258
1259     for (int j = 0; j < NRocs[i]; j++) {
1260       fprintf(outfile, "ROC%d level 0 Channel  %d :%d\n", j, i + 1, ROC_L0[i][j]);
1261       fprintf(outfile, "ROC%d level 1 Channel  %d :%d\n", j, i + 1, ROC_L1[i][j]);
1262       fprintf(outfile, "ROC%d level 2 Channel  %d :%d\n", j, i + 1, ROC_L2[i][j]);
1263       fprintf(outfile, "ROC%d level 3 Channel  %d :%d\n", j, i + 1, ROC_L3[i][j]);
1264       fprintf(outfile, "ROC%d level 4 Channel  %d :%d\n", j, i + 1, ROC_L4[i][j]);
1265     }
1266
1267     fprintf(outfile, "TRLR level 0 Channel %d:%d\n", i + 1, TRL_L0[i]);
1268     fprintf(outfile, "TRLR level 1 Channel %d:%d\n", i + 1, TRL_L1[i]);
1269     fprintf(outfile, "TRLR level 2 Channel %d:%d\n", i + 1, TRL_L2[i]);
1270     fprintf(outfile, "TRLR level 3 Channel %d:%d\n", i + 1, TRL_L3[i]);
1271     fprintf(outfile, "TRLR level 4 Channel %d:%d\n", i + 1, TRL_L4[i]);
1272   }
1273
1274   //These bits turn off(1) and on(0) channels
1275   fprintf(outfile, "Channel Enbable bits chnls 1-9  (on = 0):0x%x\n", Ncntrl);
1276   fprintf(outfile, "Channel Enbable bits chnls 10-18(on = 0):0x%x\n", NCcntrl);
1277   fprintf(outfile, "Channel Enbable bits chnls 19-27(on = 0):0x%x\n", SCcntrl);
1278   fprintf(outfile, "Channel Enbable bits chnls 28-36(on = 0):0x%x\n", Scntrl);
1279
1280   //These are delays to the TTCrx
1281   fprintf(outfile, "TTCrx Coarse Delay Register 2:%d\n", CoarseDel);
1282   fprintf(outfile, "TTCrc      ClkDes2 Register 3:0x%x\n", ClkDes2);
1283   fprintf(outfile, "TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", FineDes2Del);
1284
1285   // Control register
1286   fprintf(outfile, "Center Chip Control Reg:0x%x\n", Ccntrl);
1287   fprintf(outfile, "Initial Slink DAQ mode:%d\n", modeRegister);
1288
1289   //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
1290   fprintf(outfile, "Channel ADC Gain bits chnls  1-12(1Vpp = 0):0x%x\n", Nadcg);
1291   fprintf(outfile, "Channel ADC Gain bits chnls 13-20(1Vpp = 0):0x%x\n", NCadcg);
1292   fprintf(outfile, "Channel ADC Gain bits chnls 21-28(1Vpp = 0):0x%x\n", SCadcg);
1293   fprintf(outfile, "Channel ADC Gain bits chnls 29-36(1Vpp = 0):0x%x\n", Sadcg);
1294
1295   //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
1296   fprintf(outfile, "Channel Baseline Enbable chnls 1-9  (on = (0x1ff<<16)+):0x%x\n", Nbaseln);
1297   fprintf(outfile, "Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):0x%x\n", NCbaseln);
1298   fprintf(outfile, "Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):0x%x\n", SCbaseln);
1299   fprintf(outfile, "Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):0x%x\n", Sbaseln);
1300
1301   //These bits set TBM trailer mask (common by FPGA)
1302   fprintf(outfile, "TBM trailer mask chnls 1-9  (0xff = all masked):0x%x\n", N_TBMmask);
1303   fprintf(outfile, "TBM trailer mask chnls 10-18(0xff = all masked):0x%x\n", NC_TBMmask);
1304   fprintf(outfile, "TBM trailer mask chnls 19-27(0xff = all masked):0x%x\n", SC_TBMmask);
1305   fprintf(outfile, "TBM trailer mask chnls 28-36(0xff = all masked):0x%x\n", S_TBMmask);
1306
1307   //These bits set the Private fill/gap word value (common by FPGA)
1308   fprintf(outfile, "Private 8 bit word chnls 1-9  :0x%x\n", N_Pword);
1309   fprintf(outfile, "Private 8 bit word chnls 10-18:0x%x\n", NC_Pword);
1310   fprintf(outfile, "Private 8 bit word chnls 19-27:0x%x\n", SC_Pword);
1311   fprintf(outfile, "Private 8 bit word chnls 28-36:0x%x\n", S_Pword);
1312
1313   //These bit sets the special dac mode for random triggers
1314   fprintf(outfile, "Special Random testDAC mode (on = 0x1, off=0x0):0x%x\n", SpecialDac);
1315
1316   //These bits set the number of Out of consecutive out of sync events until a TTs OOs
1317   fprintf(outfile, "Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", Ooslvl);
1318
1319   //These bits set the number of Empty events until a TTs Error
1320   fprintf(outfile, "Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", Errlvl);
1321
1322   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
1323   fprintf(outfile, "N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Nfifo1Bzlvl);
1324
1325   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
1326   fprintf(outfile, "NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", NCfifo1Bzlvl);
1327
1328   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
1329   fprintf(outfile, "SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", SCfifo1Bzlvl);
1330
1331   //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
1332   fprintf(outfile, "S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Sfifo1Bzlvl);
1333
1334   //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
1335   fprintf(outfile, "Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", fifo3Wrnlvl);
1336
1337   fprintf(outfile, "FED Master delay 0=0,1=32,2=48,3=64:%d\n", FedTTCDelay);
1338
1339   fprintf(outfile, "TTCrx Register 0 fine delay ClkDes1:%d\n", FineDes1Del);
1340
1341   int checkword = 20211;
1342
1343   fprintf(outfile, "Params FED file check word:%d\n", checkword);
1344
1345   //These bits set the hit limit in fifo-1 for an event
1346   fprintf(outfile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1347           N_hitlimit);  //ch 1-9
1348
1349   fprintf(outfile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1350           NC_hitlimit);  //ch 10-18
1351
1352   fprintf(outfile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1353           SC_hitlimit);  //ch 19-27
1354
1355   fprintf(outfile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1356           S_hitlimit);  //ch 28-36
1357
1358   //These bits allow a ROC to be skipped (1/fpga)
1359   fprintf(outfile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
1360
1361   fprintf(outfile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
1362
1363   fprintf(outfile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
1364
1365   fprintf(outfile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
1366
1367   fprintf(outfile, "Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", BusyWhenBehind);
1368
1369   fprintf(outfile, "D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):0x%x\n", FeatureRegister);
1370
1371   fprintf(outfile, "Limit for fifo-2 almost full (point for the TTS flag):0x%x\n", FIFO2Limit);
1372
1373   fprintf(outfile, "Limit for consecutive timeout OR OOSs:%d\n", TimeoutOROOSLimit);
1374
1375   fprintf(outfile, "Turn off filling of lastdac fifos(exc 1st ROC):%d\n", LastDacOff);
1376
1377   fprintf(outfile, "Number of simulated hits per ROC for internal generator:%d\n", SimHitsPerRoc);
1378
1379   fprintf(outfile, "Miniumum hold time for busy (changing definition):%d\n", BusyHoldMin);
1380
1381   fprintf(outfile, "Trigger Holdoff in units of 25us(0=none):%d\n", TriggerHoldoff);
1382
1383   fprintf(outfile, "Spare fedcard input 1:%d\n", SPARE1);
1384   fprintf(outfile, "Spare fedcard input 2:%d\n", SPARE2);
1385   fprintf(outfile, "Spare fedcard input 3:%d\n", SPARE3);
1386   fprintf(outfile, "Spare fedcard input 4:%d\n", SPARE4);
1387   fprintf(outfile, "Spare fedcard input 5:%d\n", SPARE5);
1388   fprintf(outfile, "Spare fedcard input 6:%d\n", SPARE6);
1389   fprintf(outfile, "Spare fedcard input 7:%d\n", SPARE7);
1390   fprintf(outfile, "Spare fedcard input 8:%d\n", SPARE8);
1391   fprintf(outfile, "Spare fedcard input 9:%d\n", SPARE9);
1392   fprintf(outfile, "Spare fedcard input 10:%d\n", SPARE10);
1393
1394   fclose(outfile);
1395 }
1396
1397 //=============================================================================================
1398 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key,
1399                                   int version,
1400                                   std::string path,
1401                                   std::ofstream *fedstream,
1402                                   std::ofstream *rocstream,
1403                                   std::ofstream *tbmstream) const {
1404   std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t    ";
1405   std::stringstream fedfullPath;
1406   std::stringstream rocfullPath;
1407   std::stringstream tbmfullPath;
1408
1409   // modified by MR on 05-08-2008 16:50:28
1410   // FED MAIN XML FILE
1411   fedfullPath << path << "/FedConfiguration_Template_" << PixelTimeFormatter::getmSecTime() << ".xml";
1412   std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fedfullPath.str() << "" << std::endl;
1413
1414   fedstream->open(fedfullPath.str().c_str());
1415
1416   *fedstream << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl;
1417   *fedstream << "<ROOT xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'>" << std::endl;
1418   *fedstream << "" << std::endl;
1419   *fedstream << " <HEADER>" << std::endl;
1420   *fedstream << "  <HINTS mode='load-as-group' /> " << std::endl;
1421   *fedstream << "  <TYPE>" << std::endl;
1422   *fedstream << "   <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1423   *fedstream << "   <NAME>Pixel FED Configuration</NAME>" << std::endl;
1424   *fedstream << "  </TYPE>" << std::endl;
1425   *fedstream << "  <RUN>" << std::endl;
1426   *fedstream << "   <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1427   *fedstream << "   <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1428   *fedstream << "   <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1429   *fedstream << "   <LOCATION>CERN P5</LOCATION>" << std::endl;
1430   *fedstream << "  </RUN>" << std::endl;
1431   *fedstream << " </HEADER>" << std::endl;
1432   *fedstream << "" << std::endl;
1433   *fedstream << " <DATA_SET>" << std::endl;
1434   *fedstream << "" << std::endl;
1435   *fedstream << "  <VERSION>" << version << "</VERSION>" << std::endl;
1436   *fedstream << "  <COMMENT_DESCRIPTION>" << getComment() << "</COMMENT_DESCRIPTION>" << std::endl;
1437   *fedstream << "  <CREATED_BY_USER>" << getAuthor() << "</CREATED_BY_USER>" << std::endl;
1438   *fedstream << "" << std::endl;
1439   *fedstream << "  <PART>" << std::endl;
1440   *fedstream << "   <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1441   *fedstream << "   <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1442   *fedstream << "  </PART>" << std::endl;
1443
1444   // ROC LEVELS MAIN XML FILE
1445   rocfullPath << path << "/Pixel_RocAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml";
1446   std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << rocfullPath.str() << "" << std::endl;
1447
1448   rocstream->open(rocfullPath.str().c_str());
1449
1450   *rocstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl;
1451   *rocstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl;
1452   *rocstream << "" << std::endl;
1453   *rocstream << " <HEADER>" << std::endl;
1454   *rocstream << "  <HINTS mode='only-det-root,load-as-group'/>" << std::endl;
1455   *rocstream << "  <TYPE>" << std::endl;
1456   *rocstream << "   <EXTENSION_TABLE_NAME>ROC_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl;
1457   *rocstream << "   <NAME>ROC Analog Levels</NAME>" << std::endl;
1458   *rocstream << "  </TYPE>" << std::endl;
1459   *rocstream << "  <RUN>" << std::endl;
1460   *rocstream << "   <RUN_TYPE>ROC Analog Levels</RUN_TYPE>" << std::endl;
1461   *rocstream << "   <RUN_NUMBER>1</RUN_NUMBER>                      " << std::endl;
1462   *rocstream << "   <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1463   *rocstream << "   <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl;
1464   *rocstream << "   <LOCATION>CERN</LOCATION> " << std::endl;
1465   *rocstream << "   <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl;
1466   *rocstream << "  </RUN>" << std::endl;
1467   *rocstream << " </HEADER>" << std::endl;
1468   *rocstream << "" << std::endl;
1469   *rocstream << "  <DATA_SET>" << std::endl;
1470   *rocstream << "   <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl;
1471   *rocstream << "   <VERSION>" << version << "</VERSION>" << std::endl;
1472   *rocstream << "   " << std::endl;
1473   *rocstream << "   <PART>" << std::endl;
1474   *rocstream << "           <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl;
1475   *rocstream << "           <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1476   *rocstream << "   </PART>" << std::endl;
1477
1478   // TBM LEVELS MAIN XML FILE
1479   tbmfullPath << path << "/Pixel_TbmAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml";
1480   std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << tbmfullPath.str() << "" << std::endl;
1481
1482   tbmstream->open(tbmfullPath.str().c_str());
1483
1484   *tbmstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl;
1485   *tbmstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl;
1486   *tbmstream << "" << std::endl;
1487   *tbmstream << " <HEADER>" << std::endl;
1488   *tbmstream << "  <HINTS mode='only-det-root,load-as-group' />" << std::endl;
1489   *tbmstream << "  <TYPE>" << std::endl;
1490   *tbmstream << "   <EXTENSION_TABLE_NAME>TBM_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl;
1491   *tbmstream << "   <NAME>TBM Analog Levels</NAME>" << std::endl;
1492   *tbmstream << "  </TYPE>" << std::endl;
1493   *tbmstream << "  <RUN>" << std::endl;
1494   *tbmstream << "   <RUN_TYPE>TBM Analog Levels</RUN_TYPE>" << std::endl;
1495   *tbmstream << "   <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1496   *tbmstream << "   <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1497   *tbmstream << "   <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl;
1498   *tbmstream << "   <LOCATION>CERN</LOCATION> " << std::endl;
1499   *tbmstream << "   <COMMENT_DESCRIPTION>TBM Analog Levels</COMMENT_DESCRIPTION>" << std::endl;
1500   *tbmstream << "  </RUN>" << std::endl;
1501   *tbmstream << " </HEADER>" << std::endl;
1502   *tbmstream << "" << std::endl;
1503   *tbmstream << "  <DATA_SET>" << std::endl;
1504   *tbmstream << "   <VERSION>" << version << "</VERSION>" << std::endl;
1505   *tbmstream << "   " << std::endl;
1506   *tbmstream << "   <PART>" << std::endl;
1507   *tbmstream << "    <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl;
1508   *tbmstream << "    <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1509   *tbmstream << "   </PART>" << std::endl;
1510 }
1511
1512 //=============================================================================================
1513 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key, int version, std::string path, std::ofstream *out) const {
1514   std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t    ";
1515   std::stringstream fullPath;
1516
1517   fullPath << path << "/fedcard_" << PixelTimeFormatter::getmSecTime() << ".xml";
1518   std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fullPath.str() << "" << std::endl;
1519
1520   out->open(fullPath.str().c_str());
1521
1522   *out << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl;
1523   *out << "<ROOT>" << std::endl;
1524   *out << "" << std::endl;
1525   *out << " <HEADER>" << std::endl;
1526   *out << "  <TYPE>" << std::endl;
1527   *out << "   <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1528   *out << "   <NAME>Pixel FED Configuration</NAME>" << std::endl;
1529   *out << "  </TYPE>" << std::endl;
1530   *out << "  <RUN>" << std::endl;
1531   *out << "   <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1532   *out << "   <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1533   *out << "   <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1534   *out << "   <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1535   *out << "   <LOCATION>CERN TAC</LOCATION>" << std::endl;
1536   *out << "   <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl;
1537   *out << "  </RUN>" << std::endl;
1538   *out << " </HEADER>" << std::endl;
1539   *out << "" << std::endl;
1540   *out << " <DATA_SET>" << std::endl;
1541   *out << "" << std::endl;
1542   *out << "  <VERSION>" << version << "</VERSION>" << std::endl;
1543   *out << "  <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1544   *out << "" << std::endl;
1545   *out << "  <PART>" << std::endl;
1546   *out << "   <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1547   *out << "   <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1548   *out << "  </PART>" << std::endl;
1549 }
1550 //=============================================================================================
1551 void PixelFEDCard::writeXML(std::ofstream *out) const {
1552   std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t    ";
1553
1554   *out << "  <DATA>" << std::endl;
1555   *out << " " << std::endl;
1556   *out << "   <PXLFED_NAME>PxlFED_" << fedNumber << "</PXLFED_NAME>" << std::endl;
1557   *out << "   <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl;
1558   //  *out << "   <CRATE_NUMBER>1</CRATE_NUMBER>"                                                         << std::endl ;
1559   //  *out << "   <SLOT_NUMBER>5</SLOT_NUMBER>      "                                                     << std::endl ;
1560   //  *out << "   <VME_ADDRESS>268435456</VME_ADDRESS>"                                                   << std::endl ;
1561   //  *out << "   <CRATE_LABEL>S1G03e</CRATE_LABEL>"                                                      << std::endl ;
1562   *out << "" << std::endl;
1563   *out << "   <CHANNEL_ID>1</CHANNEL_ID>" << std::endl;
1564   *out << "   <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl;
1565   *out << "   <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl;
1566   *out << "   <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl;
1567   *out << "   <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl;
1568   *out << "   <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl;
1569   *out << "   <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl;
1570   *out << "" << std::endl;
1571   *out << "   <OPT1_CAP>0</OPT1_CAP>" << std::endl;
1572   *out << "   <OPT2_CAP>0</OPT2_CAP>" << std::endl;
1573   *out << "   <OPT3_CAP>0</OPT3_CAP>" << std::endl;
1574   *out << "   <OPT1_INP>0</OPT1_INP>" << std::endl;
1575   *out << "   <OPT2_INP>0</OPT2_INP>" << std::endl;
1576   *out << "   <OPT3_INP>0</OPT3_INP>" << std::endl;
1577   *out << "   <OPT1_OUT>0</OPT1_OUT>" << std::endl;
1578   *out << "   <OPT2_OUT>0</OPT2_OUT>" << std::endl;
1579   *out << "   <OPT3_OUT>0</OPT3_OUT>" << std::endl;
1580   *out << "   <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl;
1581   *out << "   <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl;
1582   *out << "   <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl;
1583   *out << "   <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl;
1584   *out << "   <NORTH_CTRL>0</NORTH_CTRL> " << std::endl;
1585   *out << "   <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl;
1586   *out << "   <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl;
1587   *out << "   <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl;
1588   *out << "   <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl;
1589   *out << "   <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl;
1590   *out << "   <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl;
1591   *out << "   <CENTER_CTRL>0</CENTER_CTRL>" << std::endl;
1592   *out << "   <CENTER_MODE>0</CENTER_MODE>" << std::endl;
1593   *out << "   <B1_ADCGN>0</B1_ADCGN>" << std::endl;
1594   *out << "   <B2_ADCGN>0</B2_ADCGN>" << std::endl;
1595   *out << "   <B3_ADCGN>0</B3_ADCGN>" << std::endl;
1596   *out << "   <B4_ADCGN>0</B4_ADCGN>" << std::endl;
1597   *out << "   <NORTH_BADJ>330</NORTH_BADJ>" << std::endl;
1598   *out << "   <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl;
1599   *out << "   <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl;
1600   *out << "   <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl;
1601   *out << "   <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl;
1602   *out << "   <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl;
1603   *out << "   <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl;
1604   *out << "   <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl;
1605   *out << "   <NORTH_PWORD>177</NORTH_PWORD>" << std::endl;
1606   *out << "   <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl;
1607   *out << "   <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl;
1608   *out << "   <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl;
1609   *out << "   <SPECDAC>0</SPECDAC>" << std::endl;
1610   *out << "   <OOS_LVL>0</OOS_LVL>" << std::endl;
1611   *out << "   <ERR_LVL>0</ERR_LVL>" << std::endl;
1612   *out << "   <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl;
1613   *out << "   <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1614   *out << "   <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1615   *out << "   <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1616   *out << "   <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl;
1617   *out << "   <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl;
1618   *out << "   <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl;
1619   *out << "   <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl;
1620   *out << "   <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl;
1621   *out << "   <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl;
1622   *out << "   <NO_TESTREG>0</NO_TESTREG>" << std::endl;
1623   *out << "   <NC_TESTREG>0</NC_TESTREG>" << std::endl;
1624   *out << "   <SC_TESTREG>0</SC_TESTREG>" << std::endl;
1625   *out << "   <SO_TESTREG>0</SO_TESTREG>" << std::endl;
1626   *out << "   <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl;
1627   *out << "   <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl;
1628   *out << "   <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl;
1629   *out << "   <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl;
1630   *out << "   <LASTDACOFF>0</LASTDACOFF>" << std::endl;
1631   *out << "   <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl;
1632   *out << "   <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl;
1633   *out << "   <SPARE1>0</SPARE1>" << std::endl;
1634   *out << "   <SPARE2>0</SPARE2>" << std::endl;
1635   *out << "   <SPARE3>0</SPARE3>" << std::endl;
1636   *out << "   <SPARE4>0</SPARE4>" << std::endl;
1637   *out << "   <SPARE5>0</SPARE5>" << std::endl;
1638   *out << "   <SPARE6>0</SPARE6>" << std::endl;
1639   *out << "   <SPARE7>0</SPARE7>" << std::endl;
1640   *out << "   <SPARE8>0</SPARE8>" << std::endl;
1641   *out << "   <SPARE9>0</SPARE9>" << std::endl;
1642   *out << "   <SPARE10>0</SPARE10>" << std::endl;
1643   *out << " " << std::endl;
1644   *out << "  </DATA>" << std::endl;
1645   *out << " " << std::endl;
1646 }
1647
1648 //=============================================================================================
1649 void PixelFEDCard::writeXML(std::ofstream *fedstream, std::ofstream *rocstream, std::ofstream *tbmstream) const {
1650   std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t    ";
1651
1652   for (int i = 0; i < 36; i++) {
1653     *fedstream << "  <DATA>" << std::endl;
1654     *fedstream << " " << std::endl;
1655     *fedstream << "   <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1656     *fedstream << "   <VME_ADDRS_HEX>0x" << hex << FEDBASE_0 << dec << "</VME_ADDRS_HEX>" << std::endl;
1657     *fedstream << "" << std::endl;
1658     *fedstream << "   <CHANNEL_ID>" << i + 1 << "</CHANNEL_ID>" << std::endl;
1659     *fedstream << "   <NUM_ROCS>" << NRocs[i] << "</NUM_ROCS>" << std::endl;
1660     *fedstream << "   <CHAN_OFFST_DAC>" << offs_dac[i] << "</CHAN_OFFST_DAC>" << std::endl;
1661     *fedstream << "   <CHAN_DELAY>" << DelayCh[i] << "</CHAN_DELAY>" << std::endl;
1662     *fedstream << "   <CHAN_BHIGH>" << BlackHi[i] << "</CHAN_BHIGH>" << std::endl;
1663     *fedstream << "   <CHAN_BLOW>" << BlackLo[i] << "</CHAN_BLOW>" << std::endl;
1664     *fedstream << "   <CHAN_UB>" << Ublack[i] << "</CHAN_UB>" << std::endl;
1665     *fedstream << "" << std::endl;
1666     *fedstream << "   <OPT1_CAP>" << opt_cap[0] << "</OPT1_CAP>" << std::endl;
1667     *fedstream << "   <OPT2_CAP>" << opt_cap[1] << "</OPT2_CAP>" << std::endl;
1668     *fedstream << "   <OPT3_CAP>" << opt_cap[2] << "</OPT3_CAP>" << std::endl;
1669     *fedstream << "   <OPT1_INP>" << opt_inadj[0] << "</OPT1_INP>" << std::endl;
1670     *fedstream << "   <OPT2_INP>" << opt_inadj[1] << "</OPT2_INP>" << std::endl;
1671     *fedstream << "   <OPT3_INP>" << opt_inadj[2] << "</OPT3_INP>" << std::endl;
1672     *fedstream << "   <OPT1_OUT>" << opt_ouadj[0] << "</OPT1_OUT>" << std::endl;
1673     *fedstream << "   <OPT2_OUT>" << opt_ouadj[1] << "</OPT2_OUT>" << std::endl;
1674     *fedstream << "   <OPT3_OUT>" << opt_ouadj[2] << "</OPT3_OUT>" << std::endl;
1675     *fedstream << "   <NORTH_CLKPHB>" << clkphs1_9 << "</NORTH_CLKPHB>" << std::endl;
1676     *fedstream << "   <NORTHCENTER_CLKPHB>" << clkphs10_18 << "</NORTHCENTER_CLKPHB>" << std::endl;
1677     *fedstream << "   <SOUTHCENTER_CLKPHB>" << clkphs19_27 << "</SOUTHCENTER_CLKPHB>" << std::endl;
1678     *fedstream << "   <SOUTH_CLKPHB>" << clkphs28_36 << "</SOUTH_CLKPHB>" << std::endl;
1679     *fedstream << "   <NORTH_CTRL>" << Ncntrl << "</NORTH_CTRL> " << std::endl;
1680     *fedstream << "   <NORTHCENTER_CTRL>" << NCcntrl << "</NORTHCENTER_CTRL>" << std::endl;
1681     *fedstream << "   <SOUTHCENTER_CTRL>" << SCcntrl << "</SOUTHCENTER_CTRL>" << std::endl;
1682     *fedstream << "   <SOUTH_CTRL>" << Scntrl << "</SOUTH_CTRL>" << std::endl;
1683     *fedstream << "   <REG0_TTCRX_FDLA>" << FineDes1Del << "</REG0_TTCRX_FDLA>" << std::endl;
1684     *fedstream << "   <REG1_TTCRX_FDLA>" << FineDes2Del << "</REG1_TTCRX_FDLA>" << std::endl;
1685     *fedstream << "   <REG2_TTCRX_CDLA>" << CoarseDel << "</REG2_TTCRX_CDLA>" << std::endl;
1686     *fedstream << "   <REG3_TTCRX_CLKD2>" << ClkDes2 << "</REG3_TTCRX_CLKD2>" << std::endl;
1687     *fedstream << "   <CENTER_CTRL>" << Ccntrl << "</CENTER_CTRL>" << std::endl;
1688     *fedstream << "   <CENTER_MODE>" << modeRegister << "</CENTER_MODE>" << std::endl;
1689     *fedstream << "   <B1_ADCGN>" << Nadcg << "</B1_ADCGN>" << std::endl;
1690     *fedstream << "   <B2_ADCGN>" << NCadcg << "</B2_ADCGN>" << std::endl;
1691     *fedstream << "   <B3_ADCGN>" << SCadcg << "</B3_ADCGN>" << std::endl;
1692     *fedstream << "   <B4_ADCGN>" << Sadcg << "</B4_ADCGN>" << std::endl;
1693     //       std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << Nbaseln << std::endl ;
1694     //       std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << std::hex << Nbaseln << std::dec << std::endl ;
1695     *fedstream << "   <NORTH_BADJ>" << Nbaseln << "</NORTH_BADJ>" << std::endl;
1696     *fedstream << "   <NORTHCENTER_BADJ>" << NCbaseln << "</NORTHCENTER_BADJ>" << std::endl;
1697     *fedstream << "   <SOUTHCENTER_BADJ>" << SCbaseln << "</SOUTHCENTER_BADJ>" << std::endl;
1698     *fedstream << "   <SOUTH_BADJ>" << Sbaseln << "</SOUTH_BADJ>" << std::endl;
1699     *fedstream << "   <NORTH_TBMMASK>" << N_TBMmask << "</NORTH_TBMMASK>" << std::endl;
1700     *fedstream << "   <NORTHCENTER_TBMMASK>" << NC_TBMmask << "</NORTHCENTER_TBMMASK>" << std::endl;
1701     *fedstream << "   <SOUTHCENTER_TBMMASK>" << SC_TBMmask << "</SOUTHCENTER_TBMMASK>" << std::endl;
1702     *fedstream << "   <SOUTH_TBMMASK>" << S_TBMmask << "</SOUTH_TBMMASK>" << std::endl;
1703     *fedstream << "   <NORTH_PWORD>" << N_Pword << "</NORTH_PWORD>" << std::endl;
1704     *fedstream << "   <NORTHCENTER_PWORD>" << NC_Pword << "</NORTHCENTER_PWORD>" << std::endl;
1705     *fedstream << "   <SOUTHCENTER_PWORD>" << SC_Pword << "</SOUTHCENTER_PWORD>" << std::endl;
1706     *fedstream << "   <SOUTH_PWORD>" << S_Pword << "</SOUTH_PWORD>" << std::endl;
1707     *fedstream << "   <SPECDAC>" << SpecialDac << "</SPECDAC>" << std::endl;
1708     *fedstream << "   <OOS_LVL>" << Ooslvl << "</OOS_LVL>" << std::endl;
1709     *fedstream << "   <ERR_LVL>" << Errlvl << "</ERR_LVL>" << std::endl;
1710     *fedstream << "   <NORTH_FIFO1_BZ_LVL>" << Nfifo1Bzlvl << "</NORTH_FIFO1_BZ_LVL>" << std::endl;
1711     *fedstream << "   <NORTHCENTER_FIFO1_BZ_LVL>" << NCfifo1Bzlvl << "</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1712     *fedstream << "   <SOUTHCENTER_FIFO1_BZ_LVL>" << SCfifo1Bzlvl << "</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1713     *fedstream << "   <SOUTH_FIFO1_BZ_LVL>" << Sfifo1Bzlvl << "</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1714     *fedstream << "   <FIFO3_WRN_LVL>" << fifo3Wrnlvl << "</FIFO3_WRN_LVL>" << std::endl;
1715     *fedstream << "   <FED_MASTER_DELAY>" << FedTTCDelay << "</FED_MASTER_DELAY>" << std::endl;
1716     *fedstream << "   <NO_HITLIMIT>" << N_hitlimit << "</NO_HITLIMIT>" << std::endl;
1717     *fedstream << "   <NC_HITLIMIT>" << NC_hitlimit << "</NC_HITLIMIT>" << std::endl;
1718     *fedstream << "   <SC_HITLIMIT>" << SC_hitlimit << "</SC_HITLIMIT>" << std::endl;
1719     *fedstream << "   <SO_HITLIMIT>" << S_hitlimit << "</SO_HITLIMIT>" << std::endl;
1720     *fedstream << "   <NO_TESTREG>" << N_testreg << "</NO_TESTREG>" << std::endl;
1721     *fedstream << "   <NC_TESTREG>" << NC_testreg << "</NC_TESTREG>" << std::endl;
1722     *fedstream << "   <SC_TESTREG>" << SC_testreg << "</SC_TESTREG>" << std::endl;
1723     *fedstream << "   <SO_TESTREG>" << S_testreg << "</SO_TESTREG>" << std::endl;
1724     *fedstream << " <BUSYWHENBEHIND>" << BusyWhenBehind << "</BUSYWHENBEHIND>" << std::endl;
1725     *fedstream << " <BUSYHOLDMIN>" << BusyHoldMin << "</BUSYHOLDMIN>" << std::endl;
1726     *fedstream << " <FEATUREREGISTER>" << FeatureRegister << "</FEATUREREGISTER>" << std::endl;
1727     *fedstream << " <FIFO2LIMIT>" << FIFO2Limit << "</FIFO2LIMIT>" << std::endl;
1728     *fedstream << " <LASTDACOFF>" << LastDacOff << "</LASTDACOFF>" << std::endl;
1729     *fedstream << " <SIMHITSPERROC>" << SimHitsPerRoc << "</SIMHITSPERROC>" << std::endl;
1730     *fedstream << " <TIMEOUTOROOSLIMIT>" << TimeoutOROOSLimit << "</TIMEOUTOROOSLIMIT>" << std::endl;
1731     *fedstream << " <TRIGGERHOLDOFF>" << TriggerHoldoff << "</TRIGGERHOLDOFF>" << std::endl;
1732     *fedstream << " <SPARE1>" << SPARE1 << "</SPARE1>" << std::endl;
1733     *fedstream << " <SPARE2>" << SPARE2 << "</SPARE2>" << std::endl;
1734     *fedstream << " <SPARE3>" << SPARE3 << "</SPARE3>" << std::endl;
1735     *fedstream << " <SPARE4>" << SPARE4 << "</SPARE4>" << std::endl;
1736     *fedstream << " <SPARE5>" << SPARE5 << "</SPARE5>" << std::endl;
1737     *fedstream << " <SPARE6>" << SPARE6 << "</SPARE6>" << std::endl;
1738     *fedstream << " <SPARE7>" << SPARE7 << "</SPARE7>" << std::endl;
1739     *fedstream << " <SPARE8>" << SPARE8 << "</SPARE8>" << std::endl;
1740     *fedstream << " <SPARE9>" << SPARE9 << "</SPARE9>" << std::endl;
1741     *fedstream << " <SPARE10>" << SPARE10 << "</SPARE10>" << std::endl;
1742     *fedstream << " " << std::endl;
1743     *fedstream << "  </DATA>" << std::endl;
1744     *fedstream << " " << std::endl;
1745   }
1746
1747   //ROC & TBM LEVELS
1748   for (int i = 0; i < 36; i++) {
1749     for (int j = 0; j < NRocs[i]; j++) {
1750       *rocstream << "" << std::endl;
1751       *rocstream << "   <DATA>" << std::endl;
1752       *rocstream << "    <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1753       *rocstream << "    <FED_CHAN>" << i + 1 << "</FED_CHAN>" << std::endl;
1754       *rocstream << "    <FED_ROC_NUM>" << j << "</FED_ROC_NUM>" << std::endl;
1755       *rocstream << "    <ROC_L0>" << ROC_L0[i][j] << "</ROC_L0>" << std::endl;
1756       *rocstream << "    <ROC_L1>" << ROC_L1[i][j] << "</ROC_L1>" << std::endl;
1757       *rocstream << "    <ROC_L2>" << ROC_L2[i][j] << "</ROC_L2>" << std::endl;
1758       *rocstream << "    <ROC_L3>" << ROC_L3[i][j] << "</ROC_L3>" << std::endl;
1759       *rocstream << "    <ROC_L4>" << ROC_L4[i][j] << "</ROC_L4>" << std::endl;
1760       *rocstream << "   </DATA>" << std::endl << std::endl;
1761       *rocstream << " " << std::endl;
1762     }
1763
1764     *tbmstream << "" << std::endl;
1765     *tbmstream << "  <DATA>" << std::endl;
1766     *tbmstream << "   <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1767     *tbmstream << "   <FED_CHAN>" << i + 1 << "</FED_CHAN>" << std::endl;
1768     *tbmstream << "   <TBMA_HEAD_L0>" << TBM_L0[i] << "</TBMA_HEAD_L0>" << std::endl;
1769     *tbmstream << "   <TBMA_HEAD_L1>" << TBM_L1[i] << "</TBMA_HEAD_L1>" << std::endl;
1770     *tbmstream << "   <TBMA_HEAD_L2>" << TBM_L2[i] << "</TBMA_HEAD_L2>" << std::endl;
1771     *tbmstream << "   <TBMA_HEAD_L3>" << TBM_L3[i] << "</TBMA_HEAD_L3>" << std::endl;
1772     *tbmstream << "   <TBMA_HEAD_L4>" << TBM_L4[i] << "</TBMA_HEAD_L4>" << std::endl;
1773     *tbmstream << "   <TBMA_TRAIL_L0>" << TRL_L0[i] << "</TBMA_TRAIL_L0>" << std::endl;
1774     *tbmstream << "   <TBMA_TRAIL_L1>" << TRL_L1[i] << "</TBMA_TRAIL_L1>" << std::endl;
1775     *tbmstream << "   <TBMA_TRAIL_L2>" << TRL_L2[i] << "</TBMA_TRAIL_L2>" << std::endl;
1776     *tbmstream << "   <TBMA_TRAIL_L3>" << TRL_L3[i] << "</TBMA_TRAIL_L3>" << std::endl;
1777     *tbmstream << "   <TBMA_TRAIL_L4>" << TRL_L4[i] << "</TBMA_TRAIL_L4>" << std::endl;
1778     *tbmstream << "  </DATA>" << std::endl << std::endl;
1779     *tbmstream << "" << std::endl;
1780   }
1781 }
1782
1783 //=============================================================================================
1784 void PixelFEDCard::writeXMLTrailer(std::ofstream *fedstream, std::ofstream *rocstream, std::ofstream *tbmstream) const {
1785   std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t    ";
1786
1787   // Main FED
1788   *fedstream << " </DATA_SET>" << std::endl;
1789   *fedstream << "</ROOT>" << std::endl;
1790
1791   fedstream->close();
1792   std::cout << __LINE__ << "]\t" << mthn << "Data written for main fed" << std::endl;
1793
1794   // ROC LVLS
1795   *rocstream << " </DATA_SET>" << std::endl;
1796   *rocstream << "</ROOT>" << std::endl;
1797
1798   rocstream->close();
1799   std::cout << __LINE__ << "]\t" << mthn << "Data written for roc analog levels" << std::endl;
1800
1801   // TBM LVLS
1802   *tbmstream << " </DATA_SET>" << std::endl;
1803   *tbmstream << "</ROOT>" << std::endl;
1804
1805   tbmstream->close();
1806   std::cout << __LINE__ << "]\t" << mthn << "Data written for tbm analog levels" << std::endl;
1807 }
1808
1809 //=============================================================================================
1810 void PixelFEDCard::writeXMLTrailer(std::ofstream *out) const {
1811   std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t    ";
1812
1813   *out << " </DATA_SET>" << std::endl;
1814   *out << "</ROOT>" << std::endl;
1815
1816   out->close();
1817   std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl;
1818 }
1819
1820 //=============================================================================================
1821 void PixelFEDCard::writeXML(pos::PixelConfigKey key, int version, std::string path) const {
1822   std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t    ";
1823   std::stringstream fullPath;
1824
1825   fullPath << path << "/fedcard.xml";
1826   std::cout << __LINE__ << "]\t" << mthn << "Writing to: |" << fullPath.str() << "|" << std::endl;
1827
1828   std::ofstream out(fullPath.str().c_str());
1829
1830   out << "<ROOT>" << std::endl;
1831   out << "" << std::endl;
1832   out << " <HEADER>" << std::endl;
1833   out << "  <TYPE>" << std::endl;
1834   out << "   <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1835   out << "   <NAME>Pixel FED Configuration</NAME>" << std::endl;
1836   out << "  </TYPE>" << std::endl;
1837   out << "  <RUN>" << std::endl;
1838   out << "   <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1839   out << "   <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1840   out << "   <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1841   out << "   <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1842   out << "   <LOCATION>CERN TAC</LOCATION>" << std::endl;
1843   out << "   <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl;
1844   out << "  </RUN>" << std::endl;
1845   out << " </HEADER>" << std::endl;
1846   out << "" << std::endl;
1847   out << " <DATA_SET>" << std::endl;
1848   out << "" << std::endl;
1849   out << "  <VERSION>T_E_S_T</VERSION>" << std::endl;
1850   out << "  <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1851   out << "" << std::endl;
1852   out << "  <PART>" << std::endl;
1853   out << "   <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1854   out << "   <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1855   out << "  </PART>" << std::endl;
1856   out << "" << std::endl;
1857   out << "  <DATA>" << std::endl;
1858   out << "   <PXLFED_NAME>PxlFED_32</PXLFED_NAME>" << std::endl;
1859   out << "   <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl;
1860   out << "   <SLOT_NUMBER>5</SLOT_NUMBER>        " << std::endl;
1861   out << "   <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl;
1862   out << "   <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl;
1863   out << "" << std::endl;
1864   out << "   <CHANNEL_ID>1</CHANNEL_ID>" << std::endl;
1865   out << "   <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl;
1866   out << "   <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl;
1867   out << "   <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl;
1868   out << "   <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl;
1869   out << "   <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl;
1870   out << "   <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl;
1871   out << "" << std::endl;
1872   out << "   <OPT1_CAP>0</OPT1_CAP>" << std::endl;
1873   out << "   <OPT2_CAP>0</OPT2_CAP>" << std::endl;
1874   out << "   <OPT3_CAP>0</OPT3_CAP>" << std::endl;
1875   out << "   <OPT1_INP>0</OPT1_INP>" << std::endl;
1876   out << "   <OPT2_INP>0</OPT2_INP>" << std::endl;
1877   out << "   <OPT3_INP>0</OPT3_INP>" << std::endl;
1878   out << "   <OPT1_OUT>0</OPT1_OUT>" << std::endl;
1879   out << "   <OPT2_OUT>0</OPT2_OUT>" << std::endl;
1880   out << "   <OPT3_OUT>0</OPT3_OUT>" << std::endl;
1881   out << "   <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl;
1882   out << "   <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl;
1883   out << "   <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl;
1884   out << "   <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl;
1885   out << "   <NORTH_CTRL>0</NORTH_CTRL> " << std::endl;
1886   out << "   <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl;
1887   out << "   <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl;
1888   out << "   <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl;
1889   out << "   <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl;
1890   out << "   <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl;
1891   out << "   <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl;
1892   out << "   <CENTER_CTRL>0</CENTER_CTRL>" << std::endl;
1893   out << "   <CENTER_MODE>0</CENTER_MODE>" << std::endl;
1894   out << "   <B1_ADCGN>0</B1_ADCGN>" << std::endl;
1895   out << "   <B2_ADCGN>0</B2_ADCGN>" << std::endl;
1896   out << "   <B3_ADCGN>0</B3_ADCGN>" << std::endl;
1897   out << "   <B4_ADCGN>0</B4_ADCGN>" << std::endl;
1898   out << "   <NORTH_BADJ>330</NORTH_BADJ>" << std::endl;
1899   out << "   <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl;
1900   out << "   <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl;
1901   out << "   <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl;
1902   out << "   <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl;
1903   out << "   <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl;
1904   out << "   <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl;
1905   out << "   <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl;
1906   out << "   <NORTH_PWORD>177</NORTH_PWORD>" << std::endl;
1907   out << "   <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl;
1908   out << "   <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl;
1909   out << "   <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl;
1910   out << "   <SPECDAC>0</SPECDAC>" << std::endl;
1911   out << "   <OOS_LVL>0</OOS_LVL>" << std::endl;
1912   out << "   <ERR_LVL>0</ERR_LVL>" << std::endl;
1913   out << "   <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl;
1914   out << "   <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1915   out << "   <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1916   out << "   <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1917   out << "   <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl;
1918   out << "   <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl;
1919   out << "   <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl;
1920   out << "   <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl;
1921   out << "   <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl;
1922   out << "   <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl;
1923   out << "   <NO_TESTREG>0</NO_TESTREG>" << std::endl;
1924   out << "   <NC_TESTREG>0</NC_TESTREG>" << std::endl;
1925   out << "   <SC_TESTREG>0</SC_TESTREG>" << std::endl;
1926   out << "   <SO_TESTREG>0</SO_TESTREG>" << std::endl;
1927   out << "   <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl;
1928   out << "   <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl;
1929   out << "   <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl;
1930   out << "   <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl;
1931   out << "   <LASTDACOFF>0</LASTDACOFF>" << std::endl;
1932   out << "   <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl;
1933   out << "   <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl;
1934   out << "   <SPARE1>0</SPARE1>" << std::endl;
1935   out << "   <SPARE2>0</SPARE2>" << std::endl;
1936   out << "   <SPARE3>0</SPARE3>" << std::endl;
1937   out << "   <SPARE4>0</SPARE4>" << std::endl;
1938   out << "   <SPARE5>0</SPARE5>" << std::endl;
1939   out << "   <SPARE6>0</SPARE6>" << std::endl;
1940   out << "   <SPARE7>0</SPARE7>" << std::endl;
1941   out << "   <SPARE8>0</SPARE8>" << std::endl;
1942   out << "   <SPARE9>0</SPARE9>" << std::endl;
1943   out << "   <SPARE10>0</SPARE10>" << std::endl;
1944   out << "  </DATA>" << std::endl;
1945   /*
1946   out<< "  <DATA>
1947                 <OPT1_CAP>0</OPT1_CAP>
1948                 <OPT2_CAP>0</OPT2_CAP>
1949                 <OPT3_CAP>0</OPT3_CAP>
1950                 <OPT1_INP>0</OPT1_INP>
1951                 <OPT2_INP>0</OPT2_INP>
1952                 <OPT3_INP>0</OPT3_INP>
1953                 <OPT1_OUT>0</OPT1_OUT>
1954                 <OPT2_OUT>0</OPT2_OUT>
1955                 <OPT3_OUT>0</OPT3_OUT>
1956                 <NORTH_CLKPHB>511</NORTH_CLKPHB>
1957                 <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>
1958                 <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>
1959                 <SOUTH_CLKPHB>511</SOUTH_CLKPHB>
1960                 <NORTH_CTRL>0</NORTH_CTRL>
1961                 <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>
1962                 <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>
1963                 <SOUTH_CTRL>0</SOUTH_CTRL>
1964                 <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>
1965                 <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>
1966                 <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>
1967                 <CENTER_CTRL>0</CENTER_CTRL>
1968                 <CENTER_MODE>0</CENTER_MODE>
1969                 <B1_ADCGN>0</B1_ADCGN>
1970                 <B2_ADCGN>0</B2_ADCGN>
1971                 <B3_ADCGN>0</B3_ADCGN>
1972                 <B4_ADCGN>0</B4_ADCGN>
1973                 <NORTH_BADJ>330</NORTH_BADJ>
1974                 <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>
1975                 <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>
1976                 <SOUTH_BADJ>330</SOUTH_BADJ>
1977                 <NORTH_TBMMASK>2</NORTH_TBMMASK>
1978                 <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>
1979                 <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>
1980                 <SOUTH_TBMMASK>2</SOUTH_TBMMASK>
1981                 <NORTH_PWORD>177</NORTH_PWORD>
1982                 <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>
1983                 <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>
1984                 <SOUTH_PWORD>180</SOUTH_PWORD>
1985                 <SPECDAC>0</SPECDAC>
1986                 <OOS_LVL>0</OOS_LVL>
1987                 <ERR_LVL>0</ERR_LVL>
1988                 <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>
1989                 <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>
1990                 <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>
1991                 <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>
1992                 <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL>
1993         </DATA>
1994
1995   </DATA_SET>
1996   out << " </DATA_SET>"                                                                          << std::endl ;
1997   out << "</ROOT>"                                                                               << std::endl ;
1998
1999   out.close() ;
2000 */
2001   std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl;
2002 }
2003
2004 //=============================================================================================
2005 uint64_t PixelFEDCard::enabledChannels() {
2006   uint64_t channels = 0;
2007   // return a 64-bit word with low 36 bits set if a channel is enabled
2008   // if bits are set in the control registers, transfer of data from
2009   // fifo1 to fifo 2 is not done, meaning the channel is disabled.
2010   channels = (Ncntrl & 0x1ffLL);  // Add LL for SLC4, d.k. 12/07
2011   channels += (NCcntrl & 0x1ffLL) << 9;
2012   channels += (SCcntrl & 0x1ffLL) << 18;
2013   channels += (Scntrl & 0x1ffLL) << 27;
2014   return ~channels;  //bitwise complement to get enabled channels
2015 }
2016
2017 bool PixelFEDCard::useChannel(unsigned int iChannel) {
2018   assert(iChannel > 0 && iChannel < 37);
2019   return (enabledChannels() >> (iChannel - 1)) & 0x1LL;
2020 }
2021
2022 void PixelFEDCard::setChannel(unsigned int iChannel, bool mode) {
2023   assert(iChannel > 0 && iChannel < 37);
2024   long long mask = enabledChannels();
2025   long long bit = 0x1LL << (iChannel - 1);
2026   if (mode) {
2027     mask = mask | bit;
2028   } else {
2029     bit = ~bit;
2030     mask = mask & bit;
2031   }
2032   mask = ~mask;
2033   Ncntrl = (Ncntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2034   mask = mask >> 9;
2035   NCcntrl = (NCcntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2036   mask = mask >> 9;
2037   SCcntrl = (SCcntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2038   mask = mask >> 9;
2039   Scntrl = (Scntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2040 }
2041
2042 void PixelFEDCard::restoreBaselinAndChannelMasks() {
2043   Ncntrl = Ncntrl_original;
2044   NCcntrl = NCcntrl_original;
2045   SCcntrl = SCcntrl_original;
2046   Scntrl = Scntrl_original;
2047
2048   Nbaseln = Nbaseln_original;
2049   NCbaseln = NCbaseln_original;
2050   SCbaseln = SCbaseln_original;
2051   Sbaseln = Sbaseln_original;
2052 }
2053
2054 void PixelFEDCard::restoreControlAndModeRegister() {
2055   Ccntrl = Ccntrl_original;
2056   modeRegister = modeRegister_original;
2057 }
2058
2059 /* Emacs specific customization
2060    ;;; Local Variables:     ***
2061    ;;; indent-tabs-mode:nil ***
2062    ;;; c-set-style:gnu      ***
2063    ;;; End:                 ***
2064 */