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File indexing completed on 2021-02-14 13:11:31

0001 #include "DQM/SiStripCommissioningClients/interface/FedCablingHistograms.h"
0002 #include "CondFormats/SiStripObjects/interface/FedCablingAnalysis.h"
0003 #include "DQM/SiStripCommissioningAnalysis/interface/FedCablingAlgorithm.h"
0004 #include "DQM/SiStripCommissioningSummary/interface/SummaryGenerator.h"
0005 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
0006 #include "DataFormats/SiStripCommon/interface/SiStripEnumsAndStrings.h"
0007 #include "DQM/SiStripCommon/interface/ExtractTObject.h"
0008 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0009 #include <iostream>
0010 #include <sstream>
0011 #include <iomanip>
0012 #include "TProfile.h"
0013 
0014 using namespace std;
0015 using namespace sistrip;
0016 
0017 // -----------------------------------------------------------------------------
0018 /** */
0019 FedCablingHistograms::FedCablingHistograms(const edm::ParameterSet& pset, DQMStore* bei)
0020     : CommissioningHistograms(pset.getParameter<edm::ParameterSet>("FedCablingParameters"), bei, sistrip::FED_CABLING),
0021       factory_(new Factory) {
0022   LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
0023                          << " Constructing object...";
0024 }
0025 
0026 // -----------------------------------------------------------------------------
0027 /** */
0028 FedCablingHistograms::~FedCablingHistograms() {
0029   LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
0030                          << " Destructing object...";
0031 }
0032 
0033 // -----------------------------------------------------------------------------
0034 /** */
0035 void FedCablingHistograms::histoAnalysis(bool debug) {
0036   LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]";
0037 
0038   uint16_t valid = 0;
0039   HistosMap::const_iterator iter;
0040   Analyses::iterator ianal;
0041 
0042   // Clear map holding analysis objects
0043   for (ianal = data_.begin(); ianal != data_.end(); ianal++) {
0044     if (ianal->second) {
0045       delete ianal->second;
0046     }
0047   }
0048   data_.clear();
0049 
0050   // Iterate through map containing histograms
0051   for (iter = histos().begin(); iter != histos().end(); iter++) {
0052     // Check vector of histos is not empty
0053     if (iter->second.empty()) {
0054       edm::LogWarning(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
0055                                     << " Zero histograms found!";
0056       continue;
0057     }
0058 
0059     // Retrieve pointers to histos
0060     std::vector<TH1*> profs;
0061     Histos::const_iterator ihis = iter->second.begin();
0062     for (; ihis != iter->second.end(); ihis++) {
0063       TProfile* prof = ExtractTObject<TProfile>().extract((*ihis)->me_);
0064       if (prof) {
0065         profs.push_back(prof);
0066       }
0067     }
0068 
0069     // Perform histo analysis
0070     FedCablingAnalysis* anal = new FedCablingAnalysis(iter->first);
0071     FedCablingAlgorithm algo(this->pset(), anal);
0072     algo.analysis(profs);
0073     data_[iter->first] = anal;
0074     if (anal->isValid()) {
0075       valid++;
0076     }
0077   }
0078 
0079   if (!histos().empty()) {
0080     edm::LogVerbatim(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
0081                                    << " Analyzed histograms for " << histos().size() << " FED channels, of which "
0082                                    << valid << " (" << 100 * valid / histos().size() << "%) are valid.";
0083   } else {
0084     edm::LogWarning(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]"
0085                                   << " No histograms to analyze!";
0086   }
0087 }
0088 
0089 // -----------------------------------------------------------------------------
0090 /** */
0091 void FedCablingHistograms::printAnalyses() {
0092   Analyses::iterator ianal = data_.begin();
0093   Analyses::iterator janal = data_.end();
0094   for (; ianal != janal; ++ianal) {
0095     if (ianal->second) {
0096       std::stringstream ss;
0097       ianal->second->print(ss);
0098       if (ianal->second->isValid()) {
0099         LogTrace(mlDqmClient_) << ss.str();
0100       } else {
0101         edm::LogWarning(mlDqmClient_) << ss.str();
0102       }
0103     }
0104   }
0105 }
0106 
0107 // -----------------------------------------------------------------------------
0108 /** */
0109 void FedCablingHistograms::createSummaryHisto(const sistrip::Monitorable& histo,
0110                                               const sistrip::Presentation& type,
0111                                               const std::string& dir,
0112                                               const sistrip::Granularity& gran) {
0113   LogTrace(mlDqmClient_) << "[FedCablingHistograms::" << __func__ << "]";
0114 
0115   // Check view
0116   sistrip::View view = SiStripEnumsAndStrings::view(dir);
0117   if (view == sistrip::UNKNOWN_VIEW) {
0118     return;
0119   }
0120 
0121   // Analyze histograms if not done already
0122   if (data_.empty()) {
0123     histoAnalysis(false);
0124   }
0125 
0126   // Extract data to be histogrammed
0127   uint32_t xbins = factory_->init(histo, type, view, dir, gran, data_);
0128 
0129   // Create summary histogram (if it doesn't already exist)
0130   TH1* summary = histogram(histo, type, view, dir, xbins);
0131 
0132   // Fill histogram with data
0133   factory_->fill(*summary);
0134 }