Back to home page

Project CMSSW displayed by LXR

 
 

    


File indexing completed on 2022-04-27 23:38:24

0001 // system includes
0002 #include <cstdint>
0003 #include <iomanip>
0004 #include <sstream>
0005 #include <string>
0006 #include <vector>
0007 
0008 // user includes
0009 #include "CondFormats/DataRecord/interface/SiStripFedCablingRcd.h"
0010 #include "CondFormats/SiStripObjects/interface/SiStripFedCabling.h"
0011 #include "DataFormats/Common/interface/DetSetVector.h"
0012 #include "DataFormats/Common/interface/Handle.h"
0013 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
0014 #include "DataFormats/SiStripCommon/interface/SiStripEventSummary.h"
0015 #include "DataFormats/SiStripCommon/interface/SiStripFedKey.h"
0016 #include "DataFormats/SiStripDigi/interface/SiStripDigi.h"
0017 #include "DataFormats/SiStripDigi/interface/SiStripRawDigi.h"
0018 #include "FWCore/Framework/interface/ESHandle.h"
0019 #include "FWCore/Framework/interface/Event.h"
0020 #include "FWCore/Framework/interface/EventSetup.h"
0021 #include "FWCore/Framework/interface/one/EDAnalyzer.h"
0022 #include "FWCore/MessageLogger/interface/MessageLogger.h"
0023 #include "FWCore/ParameterSet/interface/ParameterSet.h"
0024 
0025 /**
0026    @class SiStripDigiAnalyzer
0027    @brief Simple class that analyzes Digis produced by RawToDigi unpacker
0028 */
0029 
0030 class SiStripTrivialDigiAnalysis {
0031 public:
0032   /** Default constructor. */
0033   SiStripTrivialDigiAnalysis()
0034       : events_(0), feds_(0), channels_(0), strips_(0), digis_(0), size_(1024), pos_(size_ + 1, 0), adc_(size_ + 1, 0) {}
0035 
0036   /** Pipes collected statistics to stringstream. */
0037   void print(std::stringstream&);
0038 
0039   // setters
0040   inline void pos(const uint16_t& pos);
0041   inline void adc(const uint16_t& adc);
0042 
0043   // getters
0044   inline const std::vector<uint16_t>& pos();
0045   inline const std::vector<uint16_t>& adc();
0046 
0047 public:
0048   uint32_t events_;
0049   uint32_t feds_;
0050   uint32_t channels_;
0051   uint32_t strips_;
0052   uint32_t digis_;
0053 
0054   const uint16_t size_;
0055 
0056 private:
0057   std::vector<uint16_t> pos_;
0058   std::vector<uint16_t> adc_;
0059 };
0060 
0061 class SiStripDigiAnalyzer : public edm::one::EDAnalyzer<> {
0062 public:
0063   SiStripDigiAnalyzer(const edm::ParameterSet&);
0064   ~SiStripDigiAnalyzer();
0065 
0066   void beginJob();
0067   void analyze(const edm::Event&, const edm::EventSetup&);
0068   void endJob();
0069 
0070 private:
0071   const edm::ESGetToken<SiStripFedCabling, SiStripFedCablingRcd> esTokenCabling_;
0072   std::string inputModuleLabel_;
0073 
0074   SiStripTrivialDigiAnalysis anal_;
0075   SiStripTrivialDigiAnalysis vr_p;
0076   SiStripTrivialDigiAnalysis pr_p;
0077   SiStripTrivialDigiAnalysis sm_p;
0078   SiStripTrivialDigiAnalysis zs_p;
0079   SiStripTrivialDigiAnalysis vr_r;
0080   SiStripTrivialDigiAnalysis pr_r;
0081   SiStripTrivialDigiAnalysis sm_r;
0082   SiStripTrivialDigiAnalysis zs_r;
0083 };
0084 
0085 void SiStripTrivialDigiAnalysis::pos(const uint16_t& pos) {
0086   if (pos < size_) {
0087     pos_[pos]++;
0088   } else {
0089     pos_[size_]++;
0090   }
0091 }
0092 
0093 void SiStripTrivialDigiAnalysis::adc(const uint16_t& adc) {
0094   if (adc < size_) {
0095     adc_[adc]++;
0096   } else {
0097     adc_[size_]++;
0098   }
0099 }
0100 
0101 const std::vector<uint16_t>& SiStripTrivialDigiAnalysis::pos() { return pos_; }
0102 const std::vector<uint16_t>& SiStripTrivialDigiAnalysis::adc() { return adc_; }
0103 
0104 using namespace std;
0105 
0106 void SiStripTrivialDigiAnalysis::print(stringstream& ss) {
0107   ss << "  [SiStripTrivialDigiAnalysis::print]"
0108      << " events: " << events_ << " feds: " << feds_ << " channels: " << channels_ << " strips: " << strips_
0109      << " digis: " << digis_;
0110   // Signal distribution (strip position vs frequency)
0111   ss << "\n  strip: ";
0112   for (uint16_t ii = 0; ii < size_; ii += (size_ / 16)) {
0113     ss << setw(4) << ii << " ";
0114   }
0115   ss << "ovrflw";
0116   ss << "\n  freq : ";
0117   for (uint16_t ii = 0; ii < size_; ii += (size_ / 16)) {
0118     ss << setw(4) << pos_[ii] << " ";
0119   }
0120   ss << "  " << setw(4) << pos_.back();
0121   // Signal landau (ADC counts vs frequency)
0122   ss << "\n  adc  : ";
0123   for (uint16_t ii = 0; ii < size_; ii += (size_ / 16)) {
0124     ss << setw(4) << ii << " ";
0125   }
0126   ss << "ovrflw";
0127   ss << "\n  freq : ";
0128   for (uint16_t ii = 0; ii < size_; ii += (size_ / 16)) {
0129     ss << setw(4) << adc_[ii] << " ";
0130   }
0131   ss << "  " << setw(4) << adc_.back();
0132   // Misc
0133   uint16_t cntr = 0;
0134   uint32_t tmp = 0;
0135   ss << "\n  adc/freq: ";
0136   for (uint16_t ii = 0; ii < size_; ii++) {
0137     if (adc_[ii]) {
0138       if (cntr < 8) {
0139         ss << ii << "/" << adc_[ii] << ", ";
0140         cntr++;
0141       }
0142       tmp += adc_[ii];
0143     }
0144   }
0145   ss << "ovrflw: " << adc_.back();
0146   ss << ", total: " << tmp;
0147 }
0148 
0149 // -----------------------------------------------------------------------------
0150 //
0151 SiStripDigiAnalyzer::SiStripDigiAnalyzer(const edm::ParameterSet& pset)
0152     : esTokenCabling_(esConsumes()), inputModuleLabel_(pset.getParameter<string>("InputModuleLabel")) {
0153   consumes<edm::DetSetVector<SiStripRawDigi> >(edm::InputTag(inputModuleLabel_, "VirginRaw"));
0154   consumes<edm::DetSetVector<SiStripRawDigi> >(edm::InputTag(inputModuleLabel_, "ProcessedRaw"));
0155   consumes<edm::DetSetVector<SiStripRawDigi> >(edm::InputTag(inputModuleLabel_, "ScopeMode"));
0156   consumes<edm::DetSetVector<SiStripDigi> >(edm::InputTag(inputModuleLabel_, "ZeroSuppressed"));
0157   consumes<SiStripEventSummary>(inputModuleLabel_);
0158   LogDebug("SiStripDigiAnalyzer") << "[SiStripDigiAnalyzer::SiStripDigiAnalyzer]"
0159                                   << " Constructing object...";
0160 }
0161 
0162 // -----------------------------------------------------------------------------
0163 //
0164 SiStripDigiAnalyzer::~SiStripDigiAnalyzer() {
0165   LogDebug("SiStripDigiAnalyzer") << "[SiStripDigiAnalyzer::~SiStripDigiAnalyzer]"
0166                                   << " Destructing object...";
0167 }
0168 
0169 // -----------------------------------------------------------------------------
0170 //
0171 void SiStripDigiAnalyzer::beginJob() { LogDebug("SiStripDigiAnalyzer") << "[SiStripDigiAnalyzer::beginJob]"; }
0172 
0173 // -----------------------------------------------------------------------------
0174 //
0175 void SiStripDigiAnalyzer::endJob() {
0176   stringstream ss;
0177   ss << "PSEUDO DIGI ANALYSIS:"
0178      << "\n";
0179   anal_.print(ss);
0180   ss << "\n";
0181   ss << "REAL DIGI (VIRGIN RAW) ANALYSIS:"
0182      << "\n";
0183   vr_r.print(ss);
0184   ss << "\n";
0185   ss << "REAL DIGI (PROCESSED RAW) ANALYSIS:"
0186      << "\n";
0187   pr_r.print(ss);
0188   ss << "\n";
0189   ss << "REAL DIGI (SCOPE MODE) ANALYSIS:"
0190      << "\n";
0191   sm_r.print(ss);
0192   ss << "\n";
0193   ss << "REAL DIGI (ZERO SUPPR) ANALYSIS:"
0194      << "\n";
0195   zs_r.print(ss);
0196   ss << "\n";
0197   LogDebug("SiStripDigiAnalyzer") << ss.str();
0198 }
0199 
0200 // -----------------------------------------------------------------------------
0201 //
0202 void SiStripDigiAnalyzer::analyze(const edm::Event& event, const edm::EventSetup& setup) {
0203   LogDebug("SiStripDigiAnalyzer") << "[" << __PRETTY_FUNCTION__ << "]"
0204                                   << " Analyzing run " << event.id().run() << " and event " << event.id().event();
0205 
0206   // Retrieve FED (reatout) and FEC (control) cabling
0207   edm::ESHandle<SiStripFedCabling> fed_cabling = setup.getHandle(esTokenCabling_);
0208 
0209   // Retrieve "real" digis
0210   edm::Handle<edm::DetSetVector<SiStripRawDigi> > vr;
0211   edm::Handle<edm::DetSetVector<SiStripRawDigi> > pr;
0212   edm::Handle<edm::DetSetVector<SiStripRawDigi> > sm;
0213   edm::Handle<edm::DetSetVector<SiStripDigi> > zs;
0214   event.getByLabel(inputModuleLabel_, "VirginRaw", vr);
0215   event.getByLabel(inputModuleLabel_, "ProcessedRaw", pr);
0216   event.getByLabel(inputModuleLabel_, "ScopeMode", sm);
0217   event.getByLabel(inputModuleLabel_, "ZeroSuppressed", zs);
0218 
0219   // Retrieve SiStripEventSummary
0220   edm::Handle<SiStripEventSummary> summary;
0221   event.getByLabel(inputModuleLabel_, summary);
0222 
0223   // Analyse digis
0224   anal_.events_++;
0225   vr_r.events_++;
0226   pr_r.events_++;
0227   sm_r.events_++;
0228   zs_r.events_++;
0229   auto ifed = fed_cabling->fedIds().begin();
0230   for (; ifed != fed_cabling->fedIds().end(); ++ifed) {
0231     anal_.feds_++;
0232     vr_r.feds_++;
0233     pr_r.feds_++;
0234     sm_r.feds_++;
0235     zs_r.feds_++;
0236     for (uint16_t ichan = 0; ichan < sistrip::FEDCH_PER_FED; ichan++) {
0237       anal_.channels_++;
0238       vr_r.channels_++;
0239       pr_r.channels_++;
0240       sm_r.channels_++;
0241       zs_r.channels_++;
0242 
0243       // Analyse digis
0244 
0245       uint32_t key = SiStripFedKey(*ifed, SiStripFedKey::feUnit(ichan), SiStripFedKey::feChan(ichan)).key();
0246 
0247       vector<edm::DetSet<SiStripRawDigi> >::const_iterator raw;
0248       vector<edm::DetSet<SiStripDigi> >::const_iterator digis;
0249 
0250       // virgin raw
0251       raw = vr->find(key);
0252       if (raw != vr->end()) {
0253         for (uint16_t istrip = 0; istrip < raw->size(); istrip++) {
0254           if (raw->data[istrip].adc()) {
0255             vr_r.strips_++;
0256             vr_r.pos(istrip);
0257             vr_r.adc(raw->data[istrip].adc());
0258           }
0259         }
0260       }
0261 
0262       // processed raw
0263       raw = pr->find(key);
0264       if (raw != pr->end()) {
0265         for (uint16_t istrip = 0; istrip < raw->size(); istrip++) {
0266           if (raw->data[istrip].adc()) {
0267             pr_r.strips_++;
0268             pr_r.pos(istrip);
0269             pr_r.adc(raw->data[istrip].adc());
0270           }
0271         }
0272       }
0273 
0274       // scope mode
0275       raw = sm->find(key);
0276       if (raw != sm->end()) {
0277         for (uint16_t istrip = 0; istrip < raw->size(); istrip++) {
0278           if (raw->data[istrip].adc()) {
0279             sm_r.strips_++;
0280             sm_r.pos(istrip);
0281             sm_r.adc(raw->data[istrip].adc());
0282           }
0283         }
0284       }
0285 
0286       // scope mode
0287       digis = zs->find(key);
0288       if (digis != zs->end()) {
0289         for (uint16_t iadc = 0; iadc < digis->size(); iadc++) {
0290           if (digis->data[iadc].adc()) {
0291             zs_r.strips_++;
0292             zs_r.pos(digis->data[iadc].strip());
0293             zs_r.adc(digis->data[iadc].adc());
0294           }
0295         }
0296       }
0297     }  // channel loop
0298   }    // fed loop
0299 }
0300 
0301 #include "FWCore/PluginManager/interface/ModuleDef.h"
0302 #include "FWCore/Framework/interface/MakerMacros.h"
0303 DEFINE_FWK_MODULE(SiStripDigiAnalyzer);