CMSSW_6_2_0_SLHC20_patch1

Changes since CMSSW_6_2_0_SLHC20:

compare to previous

  1. 6197 from @bachtis: Fix for eta 3 problem in HE reconstruction created: 2014-11-04 12:50:24 merged: 2014-11-12 04:36:15

  2. 6268 from @matz-e: Fix HCAL etaRange signature geometry created: 2014-11-07 12:48:18 merged: 2014-11-10 23:26:25

  3. 6284 from @kpedro88: reorganize HCAL aging functions alca simulation created: 2014-11-07 21:37:52 merged: 2014-11-10 23:21:32

  4. 6315 from @kpedro88: remove reduced ES hits from Shashlik configuration simulation created: 2014-11-10 17:45:35 merged: 2014-11-10 23:21:16

  5. 6148 from @bachtis: Putting the depth in the position calculator reconstruction created: 2014-10-31 16:59:24 merged: 2014-11-06 21:51:33

  6. 6114 from @sviret: AM PR optimisation l1 created: 2014-10-30 13:22:43 merged: 2014-11-06 21:46:41

  7. 6159 from @boudoul: Configuring runthematrix for high PU relval (+fix priority for injection) operations created: 2014-11-02 20:17:39 merged: 2014-11-06 21:46:34

  8. 6078 from @bendavid: Shashlik reconstruction noise model update reconstruction created: 2014-10-29 13:03:43 merged: 2014-11-03 16:47:51

  9. 6084 from @dildick: enable CSC-RPC ILT for positive endcap l1 created: 2014-10-29 16:21:58 merged: 2014-11-03 16:47:44

  10. 6098 from @osschar: Configuration load bugfix + GeometryView improvement visualization created: 2014-10-29 23:20:12 merged: 2014-11-03 16:47:36

  11. 6169 from @mark-grimes: Remove unnecessary cout from DQMStore constructor dqm created: 2014-11-03 10:44:27 merged: 2014-11-03 16:46:53

  12. 6175 from @mark-grimes: Pull request #6059 with a fix to memory handling alca simulation created: 2014-11-03 15:03:25 merged: 2014-11-03 16:41:54

  13. 6048 from @pozzobon: safety added after new digitizer l1 simulation created: 2014-10-28 14:15:53 merged: 2014-11-03 15:13:01

  14. 6057 from @jbsauvan: fix layer condition in HGCalDDDConstants::newCell() geometry created: 2014-10-28 20:17:38 merged: 2014-11-03 15:12:53

CMSDIST Changes between Tags REL/CMSSW_6_2_0_SLHC20/slc6_amd64_gcc472 and REL/CMSSW_6_2_0_SLHC20/slc6_amd64_gcc472:

compare to previous